VABA, VABD | Absolute difference, Absolute difference and
Accumulate | VABA{L} and VABD{L} |
VABS | Absolute value | V{Q}ABS and V{Q}NEG |
VACGE, VACGT | Absolute Compare Greater than or Equal, Greater
Than | VACGE and VACGT |
VACLE, VACLT | Absolute Compare Less than or Equal, Less than
(pseudo-instructionS) | VACLE and VACLT |
VADD | Add | V{Q}ADD, VADDL, VADDW, V{Q}SUB, VSUBL, and VSUBW |
VADDHN | Add, select High half | V{R}ADDHN and V{R}SUBHN |
VAND | Bitwise AND | VAND, VBIC, VEOR, VORN, and VORR (register) |
VAND | Bitwise AND (pseudo-instruction) | VAND and VORN (immediate) |
VBIC | Bitwise Bit Clear (register) | VAND, VBIC, VEOR, VORN, and VORR (register) |
VBIC | Bitwise Bit Clear (immediate) | VBIC and VORR (immediate) |
VBIF, VBIT, VBSL | Bitwise Insert if False, Insert if True, Select | VBIF, VBIT, and VBSL |
VCEQ, VCLE, VCLT | Compare Equal, Less than or Equal, Compare
Less Than | VCEQ, VCGE, VCGT, VCLE, and VCLT |
VCGE, VCGT | Compare Greater than or Equal, Greater Than | VCEQ, VCGE, VCGT, VCLE, and VCLT |
VCLE, VCLT | Compare Less than or Equal, Compare Less Than
(pseudo-instruction) | VCLE and VCLT |
VCLS, VCLZ, VCNT | Count Leading Sign bits, Count Leading Zeros,
and Count set bits | VCLS, VCLZ, and VCNT |
VCVT | Convert fixed-point or integer to floating
point, floating-point to integer or fixed-point | VCVT (between fixed-point or integer, and floating-point) |
VCVT | Convert between half-precision and single-precision
floating-point numbers | VCVT (between half-precision and single-precision floating-point) |
VDUP | Duplicate scalar to all lanes of vector | VDUP |
VEOR | Bitwise Exclusive OR | VAND, VBIC, VEOR, VORN, and VORR (register) |
VEXT | Extract | VEXT |
VHADD, VHSUB | Halving Add, Halving Subtract | V{R}HADD and VHSUB |
VLD | Vector Load | NEON load / store element and structure instructions |
VMAX, VMIN | Maximum, Minimum | VMAX, VMIN, VPMAX, and VPMIN |
VMLA, VMLS | Multiply Accumulate, Multiply Subtract (vector) | VMUL{L}, VMLA{L}, and VMLS{L} |
VMLA, VMLS | Multiply Accumulate, Multiply Subtract (by
scalar) | VMUL{L}, VMLA{L}, and VMLS{L} (by scalar) |
VMOV | Move (immediate) | VMOV, VMVN (immediate) |
VMOV | Move (register) | VMOV, VMVN (register) |
VMOVL, VMOV{U}N | Move Long, Move Narrow (register) | VMOVL, V{Q}MOVN, VQMOVUN |
VMUL | Multiply (vector) | VMUL{L}, VMLA{L}, and VMLS{L} |
VMUL | Multiply (by scalar) | VMUL{L}, VMLA{L}, and VMLS{L} (by scalar) |
VMVN | Move Negative (immediate) | VMOV, VMVN (immediate) |
VNEG | Negate | V{Q}ABS and V{Q}NEG |
VORN | Bitwise OR NOT | VAND, VBIC, VEOR, VORN, and VORR (register) |
VORN | Bitwise OR NOT (pseudo-instruction) | VAND and VORN (immediate) |
VORR | Bitwise OR (register) | VAND, VBIC, VEOR, VORN, and VORR (register) |
VORR | Bitwise OR (immediate) | VBIC and VORR (immediate) |
VPADD, VPADAL | Pairwise Add, Pairwise Add and Accumulate | VPADD{L}, VPADAL |
VPMAX, VPMIN | Pairwise Maximum, Pairwise Minimum | VMAX, VMIN, VPMAX, and VPMIN |
VQABS | Absolute value, saturate | V{Q}ABS and V{Q}NEG |
VQADD | Add, saturate | V{Q}ADD, VADDL, VADDW, V{Q}SUB, VSUBL, and VSUBW |
VQDMLAL, VQDMLSL | Saturating Doubling Multiply Accumulate, and
Multiply Subtract | VQDMULL, VQDMLAL, and VQDMLSL (by vector or by scalar) |
VQDMUL | Saturating Doubling Multiply | VQDMULL, VQDMLAL, and VQDMLSL (by vector or by scalar) |
VQDMULH | Saturating Doubling Multiply returning
High half | VQ{R}DMULH (by vector or by scalar) |
VQMOV{U}N | Saturating Move (register) | VMOVL, V{Q}MOVN, VQMOVUN |
VQNEG | Negate, saturate | V{Q}ABS and V{Q}NEG |
VQRDMULH | Saturating Doubling Multiply returning
High half | VQ{R}DMULH (by vector or by scalar) |
VQRSHL | Shift Left, Round, saturate (by signed variable) | V{Q}{R}SHL (by signed variable) |
VQRSHR | Shift Right, Round, saturate (by immediate) | VQ{R}SHR{U}N (by immediate) |
VQSHL | Shift Left, saturate (by immediate) | VSHL, VQSHL, VQSHLU, and VSHLL (by immediate) |
VQSHL | Shift Left, saturate (by signed variable) | V{Q}{R}SHL (by signed variable) |
VQSHR | Shift Right, saturate (by immediate) | VQ{R}SHR{U}N (by immediate) |
VQSUB | Subtract, saturate | V{Q}ADD, VADDL, VADDW, V{Q}SUB, VSUBL, and VSUBW |
VRADDH | Add, select High half, Round | V{R}ADDHN and V{R}SUBHN |
VRECPE | Reciprocal Estimate | VRECPE and VRSQRTE |
VRECPS | Reciprocal Step | VRECPS and VRSQRTS |
VREV | Reverse elements | VREV |
VRHADD | Halving Add, Round | V{R}HADD and VHSUB |
VRSHR, VRSRA | Shift Right and Round, Shift Right, Round,
and Accumulate (by immediate) | V{R}SHR{N}, V{R}SRA (by immediate) |
VRSQRTE | Reciprocal Square Root Estimate | VRECPE and VRSQRTE |
VRSQRTS | Reciprocal Square Root Step | VRECPS and VRSQRTS |
VRSUBH | Subtract, select High half, Round | V{R}ADDHN and V{R}SUBHN |
VSHL | Shift Left (by immediate) | VSHL, VQSHL, VQSHLU, and VSHLL (by immediate) |
VSHR | Shift Right (by immediate) | V{R}SHR{N}, V{R}SRA (by immediate) |
VSLI | Shift Left and Insert | VSLI and VSRI |
VSRA | Shift Right, Accumulate (by immediate) | V{R}SHR{N}, V{R}SRA (by immediate) |
VSRI | Shift Right and Insert | VSLI and VSRI |
VST | Vector Store | NEON load / store element and structure instructions |
VSUB | Subtract | V{Q}ADD, VADDL, VADDW, V{Q}SUB, VSUBL, and VSUBW |
VSUBH | Subtract, select High half | V{R}ADDHN and V{R}SUBHN |
VSWP | Swap vectors | VSWP |
VTBL, VTBX | Vector table look-up | VTBL, VTBX |
VTRN | Vector transpose | VTRN |
VTST | Test bits | VTST |
VUZP, VZIP | Vector interleave and de-interleave | VUZP, VZIP |
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