4.4.3. SMULxy and SMLAxy

Signed Multiply and Multiply Accumulate, with 16-bit operands and a 32-bit result and accumulator.

Syntax

SMUL<x><y>{cond} {Rd}, Rn, Rm
SMLA<x><y>{cond} Rd, Rn, Rm, Ra

where:

<x>

is either B or T. B means use the bottom half (bits [15:0]) of Rn, T means use the top half (bits [31:16]) of Rn.

<y>

is either B or T. B means use the bottom half (bits [15:0]) of Rm, T means use the top half (bits [31:16]) of Rm.

cond

is an optional condition code (see Conditional execution).

Rd

is the destination register.

Rn, Rm

are the registers holding the values to be multiplied.

Ra

is the register holding the value to be added.

Usage

Do not use r15 for Rd, Rn, Rm, or Ra.

SMULxy multiplies the 16-bit signed integers from the selected halves of Rn and Rm, and places the 32-bit result in Rd.

SMLAxy multiplies the 16-bit signed integers from the selected halves of Rn and Rm, adds the 32-bit result to the 32-bit value in Ra, and places the result in Rd.

Condition flags

These instructions do not affect the N, Z, C, or V flags.

If overflow occurs in the accumulation, SMLAxy sets the Q flag. To read the state of the Q flag, use an MRS instruction (see MRS).

Note

SMLAxy never clears the Q flag. To clear the Q flag, use an MSR instruction (see MSR).

Architectures

These ARM instructions are available in ARMv6 and above, and E variants of ARMv5T.

These 32-bit Thumb instructions are available in ARMv6T2 and above, except the ARMv7-M profile.

There are no 16-bit Thumb versions of these instructions.

Examples

    SMULTBEQ    r8, r7, r9
    SMLABBNE    r0, r2, r1, r10
    SMLABT      r0, r0, r3, r5
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