| |||

Home > ARM and Thumb Instructions > General data processing instructions > Flexible second operand |

Many ARM and Thumb-2 general data processing instructions
have a flexible second operand. This is shown as in
the descriptions of the syntax of each instruction. There are some
differences in the options permitted for

`Operand2`

has
two possible forms:

#`constant`

{,`Rm`

}`shift`

where:

`constant`

is an expression evaluating to a numeric constant. The range of constants available in ARM and Thumb-2 is not exactly the same. See

*Constants in Operand2*for details.`Rm`

is the ARM register holding the data for the second operand. The bit pattern in the register can be shifted or rotated in various ways.

`shift`

is an optional shift to be applied to

. It can be any one of:`Rm`

`ASR #`

`n`

arithmetic shift right

bits. 1 ≤`n`

≤ 32.`n`

`LSL #`

`n`

logical shift left

bits. 0 ≤`n`

≤ 31.`n`

`LSR #`

`n`

logical shift right

bits. 1 ≤`n`

≤ 32.`n`

`ROR #`

`n`

rotate right

bits. 1 ≤`n`

≤ 31.`n`

`RRX`

rotate right one bit, with extend.

`type`

`Rs`

available in ARM only, where:

`type`

is one of

`ASR`

,`LSL`

,`LSR`

,`ROR`

.`Rs`

is an ARM register supplying the shift amount. Only the least significant byte is used.

### Note

The result of the shift operation is used as

in the instruction, but`Operand2`

itself is not altered.`Rm`

In ARM instructions,

can
have any value that can be produced by rotating an 8-bit value right
by any even number of bits within a 32-bit word.`constant`

In 32-bit Thumb-2 instructions,

can
be:`constant`

Any constant that can be produced by shifting an 8-bit value left by any number of bits within a 32-bit word.

Any constant of the form

`0x00XY00XY`

.Any constant of the form

`0xXY00XY00`

.Any constant of the form

`0xXYXYXYXY`

.

In addition, in a small number of instructions,

can
take a wider range of values. These are detailed in the individual
instruction descriptions.`constant`

Constants produced by rotating an 8-bit value right by 2, 4, or 6 bits are available in ARM data processing instructions, but not in Thumb-2. All other ARM constants are also available in Thumb-2.

Arithmetic shift right by bits
divides the value contained in

`Rm`

`n`

Logical shift right by bits
divides the value contained in

`Rm`

`n`

bits
of the register are set to 0.Logical shift left by bits
multiplies the value contained in

`Rm`

`n`

bits
of the register are set to 0.Rotate right by

bits
moves the right-hand n bits of the register into the left-hand `n`

bits of
the result. At the same time, all other bits are moved right by `n`

bits
(see Figure 4.1).`n`

Rotate right with extend shifts the contents of right
by one bit. The carry flag is copied into bit[31] of

`Rm`

The old value of bit[0] of is
shifted out to the carry flag if the

`S`

The carry flag is updated to the last bit shifted out of ,
if the instruction is any one of the following:

`MOV`

,`MVN`

,`AND`

,`ORR`

,`ORN`

,`EOR`

or`BIC`

, if you use the`S`

suffix`TEQ`

or`TST`

, for which no`S`

suffix is required.

Certain pairs of instructions (`ADD`

and `SUB`

, `ADC`

and `SBC`

, `AND`

and `BIC`

, `MOV`

and `MVN`

, `CMP`

and `CMN`

)
are equivalent except for the negation or logical inversion of .

If a value of is
not available, but its logical inverse or negation is, the assembler substitutes
the other instruction of the pair and inverts or negates

`constant`

Be aware of this when comparing disassembly listings with source code.

You can use the `--diag_warning 1645`

assembler
command-line option to check when an instruction substitution occurs.