4.4.2. UMULL, UMLAL, SMULL, and SMLAL

Signed and Unsigned Long Multiply, with optional Accumulate, with 32-bit operands, and 64-bit result and accumulator.

Syntax

Op{S}{cond} RdLo, RdHi, Rn, Rm

where:

Op

is one of UMULL, UMLAL, SMULL, or SMLAL.

S

is an optional suffix available in ARM state only. If S is specified, the condition code flags are updated on the result of the operation (see Conditional execution).

cond

is an optional condition code (see Conditional execution).

RdLo, RdHi

are the destination registers. For UMLAL and SMLAL they also hold the accumulating value. RdLo and RdHi must be different registers

Rn, Rm

are ARM registers holding the operands.

Do not use r15 for RdHi, RdLo, Rn, or Rm.

Usage

The UMULL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi.

The UMLAL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers, and adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo.

The SMULL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies these integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi.

The SMLAL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies these integers, and adds the 64-bit result to the 64-bit signed integer contained in RdHi and RdLo.

Condition flags

If S is specified, these instructions:

  • update the N and Z flags according to the result

  • do not affect the C or V flags.

Architectures

These ARM instructions are available in all versions of the ARM architecture.

These 32-bit Thumb instructions are available in ARMv6T2 and above.

There are no 16-bit Thumb versions of these instructions.

Examples

    UMULL       r0, r4, r5, r6
    UMLALS      r4, r5, r3, r8
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