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Home > ARM and Thumb Instructions > Multiply instructions > UMULL, UMLAL, SMULL, and SMLAL |

Signed and Unsigned Long Multiply, with optional Accumulate, with 32-bit operands, and 64-bit result and accumulator.

{S}{`Op`

}`cond`

,`RdLo`

,`RdHi`

,`Rn`

`Rm`

where:

`Op`

is one of

`UMULL`

,`UMLAL`

,`SMULL`

, or`SMLAL`

.`S`

is an optional suffix available in ARM state only. If

is specified, the condition code flags are updated on the result of the operation (see`S`

*Conditional execution*).`cond`

is an optional condition code (see

*Conditional execution*).,`RdLo`

`RdHi`

are the destination registers. For

`UMLAL`

and`SMLAL`

they also hold the accumulating value.and`RdLo`

must be different registers`RdHi`

`Rn, Rm`

are ARM registers holding the operands.

Do not use r15 for ,

`RdLo`

`Rn`

`Rm`

The `UMULL`

instruction interprets the values from

and `Rn`

as
unsigned integers. It multiplies these integers and places the least
significant 32 bits of the result in

`RdLo`

`RdHi`

The `UMLAL`

instruction interprets the values from

and `Rn`

as
unsigned integers. It multiplies these integers, and adds the 64-bit
result to the 64-bit unsigned integer contained in

`RdHi`

`RdLo`

The `SMULL`

instruction interprets the values from

and `Rn`

as
two’s complement signed integers. It multiplies these integers and
places the least significant 32 bits of the result in

`RdLo`

`RdHi`

The `SMLAL`

instruction interprets the values from

and `Rn`

as
two’s complement signed integers. It multiplies these integers,
and adds the 64-bit result to the 64-bit signed integer contained
in

`RdHi`

`RdLo`

If * S* is specified, these instructions:

update the N and Z flags according to the result

do not affect the C or V flags.

These ARM instructions are available in all versions of the ARM architecture.

These 32-bit Thumb instructions are available in ARMv6T2 and above.

There are no 16-bit Thumb versions of these instructions.