4.2.8. LDM and STM

Load and Store Multiple registers. Any combination of registers r0 to r15 can be transferred in ARM state, but there are some restrictions in Thumb state.

See also PUSH and POP.


op{addr_mode}{cond} Rn{!}, reglist{^}



can be either:


Load Multiple registers


Store Multiple registers.


is any one of the following:


Increment address After each transfer. This is the default, and can be omitted.


Increment address Before each transfer (ARM only).


Decrement address After each transfer (ARM only).


Decrement address Before each transfer.

See Table 2.9 for stack oriented addressing mode suffixes.


is an optional condition code (see Conditional execution).


is the base register, the ARM register holding the initial address for the transfer. Rn must not be r15.


is an optional suffix. If ! is present, the final address is written back into Rn.


is a list of one or more registers to be loaded or stored, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range (see Examples).

See Restrictions on reglist in 32‑bit Thumb‑2 instructions.


is an optional suffix, available in ARM state only. You must not use it in User mode or System mode. It has the following purposes:

  • If the instruction is LDM (with any addressing mode) and reglist contains the pc (r15), in addition to the normal multiple register transfer, the SPSR is copied into the CPSR. This is for returning from exception handlers. Use this only from exception modes.

  • Otherwise, data is transferred into or out of the User mode registers instead of the current mode registers.

Restrictions on reglist in 32-bit Thumb-2 instructions

In 32-bit Thumb-2 instructions:

  • the sp cannot be in the list

  • the pc cannot be in the list in an STM instruction

  • the pc and lr cannot both be in the list in an LDM instruction

  • there must be two or more registers in the list.

If you write an STM or LDM instruction with only one register in reglist, the assembler automatically substitutes the equivalent STR or LDR instruction. Be aware of this when comparing disassembly listings with source code.

You can use the --diag_warning 1645 assembler command-line option to check when an instruction substitution occurs.

Restrictions on reglist in ARM instructions

ARM store instructions can have SP and PC in the reglist but these instructions that include SP or PC in the reglist are deprecated.

ARM load instructions can have SP and PC in the reglist but these instructions that include SP in the reglist or both PC and LR in the reglist are deprecated.

16-bit instructions

16-bit versions of a subset of these instructions are available in Thumb-2 code, and in Thumb code on pre-Thumb-2 processors.

The following restrictions apply to the 16-bit instructions:

  • all registers in reglist must be Lo registers

  • Rn must be a Lo register

  • addr_mode must be omitted (or IA), meaning increment address after each transfer

  • writeback must be specified for STM instructions

  • writeback must be specified for LDM instructions where Rn is not in the reglist.


16-bit Thumb STM instructions with writeback that specify Rn as the lowest register in the reglist are deprecated.

In addition, the PUSH and POP instructions can be expressed in this form. Some forms of PUSH and POP are also 16-bit instructions. See PUSH and POP for details.


These 16-bit instructions are not available in Thumb-2EE.

Loading to the pc

A load to the pc causes a branch to the instruction at the address loaded.

In ARMv4, bits[1:0] of the address loaded must be 0b00.

In ARMv5T and above:

  • bits[1:0] must not be 0b10

  • if bit[0] is 1, execution continues in Thumb state

  • if bit[0] is 0, execution continues in ARM state.

Loading or storing the base register, with writeback

In ARM code or pre-Thumb-2 Thumb code, if Rn is in reglist, and writeback is specified with the ! suffix:

  • if the instruction is STM or STMIA and Rn is the lowest-numbered register in reglist, the initial value of Rn is stored

  • otherwise, the loaded or stored value of Rn cannot be relied upon.

In Thumb-2 code, if Rn is in reglist, and writeback is specified with the ! suffix:

  • all 32-bit instructions are unpredictable

  • 16-bit instructions behave in the same way as in pre-Thumb-2 Thumb code, but the use of these instructions is deprecated.


    LDM     r8,{r0,r2,r9}      ; LDMIA is a synonym for LDM
    STMDB   r1!,{r3-r6,r11,r12}

Incorrect examples

    STM     r5!,{r5,r4,r9} ; value stored for r5 unpredictable 
    LDMDA   r2, {}         ; must be at least one register in list
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