4.3.7. MOV and MVN

Move and Move Not.


MOV{S}{cond} Rd, Operand2
MOV{cond} Rd, #imm16
MVN{S}{cond} Rd, Operand2



is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation (see Conditional execution).


is an optional condition code (see Conditional execution).


is the destination register.


is a flexible second operand. See Flexible second operand for details of the options.


is any value in the range 0-65535.


The MOV instruction copies the value of Operand2 into Rd.

The MVN instruction takes the value of Operand2, performs a bitwise logical NOT operation on the value, and places the result into Rd.

In certain circumstances, the assembler can substitute MVN for MOV, or MOV for MVN. Be aware of this when reading disassembly listings. See Instruction substitution for details.

Use of pc in Thumb-2 MOV and MVN

You cannot use pc (r15) for Rd, or in Operand2, in the Thumb-2 MOV or MVN instructions.

Use of pc in ARM MOV and MVN


MOV Rd,Rm syntax is allowed with Rd or Rn = pc, but not both. All other cases are deprecated.

If you use pc as Rd, the value used is the address of the instruction plus 8.

If you use pc as Rd:

  • Execution branches to the address corresponding to the result.

  • If you use the S suffix, the SPSR of the current mode is copied to the CPSR. You can use this to return from exceptions (see Chapter 6 Handling Processor Exceptions in the Developer Guide).


Do not use the S suffix when using pc as Rd in User mode or System mode. The effect of such an instruction is unpredictable, but the assembler cannot warn you at assembly time.

You cannot use pc for Rd or any operand in any data processing instruction that has a register-controlled shift (see Flexible second operand).

Condition flags

If S is specified, these instructions:

  • update the N and Z flags according to the result

  • can update the C flag during the calculation of Operand2 (see Flexible second operand)

  • do not affect the V flag.

16-bit instructions

The following forms of these instructions are available in pre-Thumb-2 Thumb code, and are 16-bit instructions when used in Thumb-2 code:

MOVS Rd, #imm

Rd must be a Lo register. imm range 0-255.


Rd and Rm must both be Lo registers.

MOV Rd, Rm

In architectures before ARMv6, either Rd or Rm, or both, must be a Hi register. In ARMv6 and above, this restriction does not apply.


The #imm16 form of the ARM instruction is available in ARMv6T2 and above. The other forms of the ARM instruction are available in all versions of the ARM architecture.

These 32-bit Thumb instructions are available in ARMv6T2 and above.

These 16-bit Thumb instructions are available in all T variants of the ARM architecture.


    MVNNE   r11, #0xF000000B ; ARM only. This constant is not available in T2.

Incorrect example

    MVN     pc,r3,ASR r0     ; pc not permitted with register controlled shift
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