4.9.4. LDC, LDC2, STC, and STC2

Transfer Data between memory and Coprocessor.


op{L}{cond} coproc, CRd, [Rn]
op{L}{cond} coproc, CRd, [Rn, #{-}offset]{!}
op{L}{cond} coproc, CRd, [Rn], #{-}offset
op{L}{cond} coproc, CRd, label



is one of LDC, LDC2, STC, or STC2.


is an optional condition code (see Conditional execution).

In ARM code, cond is not allowed for LDC2 or STC2.


is an optional suffix specifying a long transfer.


is the name of the coprocessor the instruction is for. The standard name is pn, where n is an integer in the range 0 to 15.


is the coprocessor register to load or store.


is the register on which the memory address is based. If r15 is specified, the value used is the address of the current instruction plus eight.


is an optional minus sign. If - is present, the offset is subtracted from Rn. Otherwise, the offset is added to Rn.


is an expression evaluating to a multiple of 4, in the range 0 to 1020.


is an optional suffix. If ! is present, the address including the offset is written back into Rn.


is a word-aligned program-relative expression. See Register‑relative and program‑relative expressions for more information.

label must be within 1020 bytes of the current instruction.


The use of these instructions depends on the coprocessor. See the coprocessor documentation for details.

In Thumb-2EE, if the value in the base register is zero, execution branches to the NullCheck handler at HandlerBase - 4.


LDC and STC are available in all versions of the ARM architecture.

LDC2 and STC2 are available in ARMv5T and above.

These 32-bit Thumb instructions are available in ARMv6T2 and above.

There are no 16-bit Thumb versions of these instructions.


Use of program relative addressing in the STC and STC2 instructions is deprecated.

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