4.9.2. MCR, MCR2, MCRR, and MCRR2

Move to Coprocessor from ARM Register or Registers. Depending on the coprocessor, you might be able to specify various operations in addition.

Syntax

op1{cond} coproc, #opcode1, Rt, CRn, CRm{, #opcode2}
op2{cond} coproc, #opcode3, Rt, Rt2, CRm

where:

op1

is either MCR or MCR2.

op2

is either MCRR or MCRR2.

cond

is an optional condition code (see Conditional execution). In ARM code, cond is not allowed for MCR2 or MCRR2.

coproc

is the name of the coprocessor the instruction is for. The standard name is pn, where n is an integer in the range 0 to 15.

opcode1

is a 3-bit coprocessor-specific opcode.

opcode2

is an optional 3-bit coprocessor-specific opcode.

opcode3

is a 4-bit coprocessor-specific opcode.

Rt, Rt2

are ARM source registers. MCRR or MCRR2 must not use r15.

CRn, CRm

are coprocessor registers.

Usage

The use of these instructions depends on the coprocessor. See the coprocessor documentation for details.

Architectures

The MCR ARM instruction is available in all versions of the ARM architecture.

The MCR2 ARM instruction is available in ARMv5T and above.

The MCRR ARM instruction is available in ARMv6 and above, and E variants of ARMv5T.

The MCRR2 ARM instruction is available in ARMv6 and above.

These 32-bit Thumb instructions are available in ARMv6T2 and above.

There are no 16-bit Thumb versions of these instructions.

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