4.10.4. MSR

Load an immediate constant, or the contents of a general-purpose register, into specified fields of a Program Status Register (PSR).

Syntax (except ARMv7-M and ARMv6-M)

MSR{cond} APSR_flags, #constant
MSR{cond} APSR_flags, Rm
MSR{cond} psr_fields, #constant
MSR{cond} psr_fields, Rm

where:

cond

is an optional condition code (see Conditional execution).

flags

specifies the APSR flags to be moved. flags can be one or more of:

nzcvq

ALU flags field mask, PSR[31:27] (User mode)

g

SIMD GE flags field mask, PSR[19:16] (User mode).

constant

is an expression evaluating to a numeric constant. The constant must correspond to an 8-bit pattern rotated by an even number of bits within a 32-bit word. Not available in Thumb.

Rm

is the source register.

psr

is one of:

CPSR

for use in Debug state, also deprecated synonym for APSR

SPSR

on any processor, in privileged modes only.

fields

specifies the SPSR or CPSR fields to be moved. fields can be one or more of:

c

control field mask byte, PSR[7:0] (privileged modes)

x

extension field mask byte, PSR[15:8] (privileged modes)

s

status field mask byte, PSR[23:16] (privileged modes)

f

flags field mask byte, PSR[31:24] (privileged modes).

Syntax (ARMv7-M and ARMv6-M only)

MSR{cond} psr, Rm

where:

cond

is an optional condition code (see Conditional execution).

Rm

is the source register.

psr

can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, XPSR, MSP, PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.

Usage

See MRS.

In User mode:

  • Use APSR to access condition flags, Q, or GE bits.

  • Writes to unallocated, privileged or execution state bits in the CPSR are ignored. This ensures that User mode programs cannot change to a privileged mode.

If you access the SPSR when in User or System mode, the result is unpredictable.

Condition flags

This instruction updates the flags explicitly if the APSR_nzcvq or CPSR_f field is specified.

Architectures

This ARM instruction is available in all versions of the ARM architecture.

This 32-bit Thumb instruction is available in ARMv6T2 and above.

There is no 16-bit Thumb version of this instruction.

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