4.10.2. SVC

SuperVisor Call.


SVC{cond} #immed



is an optional condition code (see Conditional execution).


is an expression evaluating to an integer in the range:

  • 0 to 224-1 (a 24-bit value) in an ARM instruction

  • 0-255 (an 8-bit value) in a 16-bit Thumb instruction.


The SVC instruction causes an exception. This means that the processor mode changes to Supervisor, the CPSR is saved to the Supervisor mode SPSR, and execution branches to the SVC vector (see Chapter 6 Handling Processor Exceptions in the Developer Guide).

immed is ignored by the processor. However, it can be retrieved by the exception handler to determine what service is being requested.


As part of the development of the ARM assembly language, the SWI instruction has been renamed to SVC. In this release of RVCT, SWI instructions disassemble to SVC, with a comment to say that this was formerly SWI.

Condition flags

This instruction does not change the flags.


This ARM instruction is available in all versions of the ARM architecture.

This 16-bit Thumb instruction is available in all T variants of the ARM architecture.

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