4.4.1. MUL, MLA, and MLS

Multiply, Multiply-Accumulate, and Multiply-Subtract, with signed or unsigned 32-bit operands, giving the least significant 32 bits of the result.

Syntax

MUL{S}{cond} {Rd}, Rn, Rm
MLA{S}{cond} Rd, Rn, Rm, Ra
MLS{cond} Rd, Rn, Rm, Ra

where:

cond

is an optional condition code (see Conditional execution).

S

is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation (see Conditional execution).

Rd

is the destination register.

Rn, Rm

are registers holding the values to be multiplied.

Ra

is a register holding the value to be added or subtracted from.

Usage

The MUL instruction multiplies the values from Rn and Rm, and places the least significant 32 bits of the result in Rd.

The MLA instruction multiplies the values from Rn and Rm, adds the value from Ra, and places the least significant 32 bits of the result in Rd.

The MLS instruction multiplies the values from Rn and Rm, subtracts the result from the value from Ra, and places the least significant 32 bits of the final result in Rd.

Do not use r15 for Rd, Rn, Rm, or Ra.

Condition flags

If S is specified, the MUL and MLA instructions:

  • update the N and Z flags according to the result

  • corrupt the C and V flag in ARMv4 and earlier

  • do not affect the C or V flag in ARMv5T and above.

Thumb instructions

The following form of the MUL instruction is available in pre-Thumb-2 Thumb code, and is a 16-bit instruction when used in Thumb-2 code:

MULS Rd, Rn, Rd

Rd and Rn must both be Lo registers.

There are no other Thumb multiply instructions that can update the condition code flags.

Architectures

The MUL and MLA ARM instructions are available in all versions of the ARM architecture.

The MLS ARM instruction is available in ARMv6T2 and above.

These 32-bit Thumb instructions are available in ARMv6T2 and above.

The MULS 16-bit Thumb instruction is available in all T variants of the ARM architecture.

Examples

    MUL     r10, r2, r5
    MLA     r10, r2, r1, r5
    MULS    r0, r2, r2
    MULLT   r2, r3, r2
    MLS     r4, r5, r6, r7
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