4.2.5. LDR (pc-relative)

Load register. The address is an offset from the pc.


See also Pseudo‑instructions.


LDR{type}{cond}{.W} Rt, label
LDRD{cond} Rt, Rt2, label        ; Doubleword



can be any one of:


unsigned Byte (Zero extend to 32 bits on loads.)


signed Byte (LDR only. Sign extend to 32 bits.)


unsigned Halfword (Zero extend to 32 bits on loads.)


signed Halfword (LDR only. Sign extend to 32 bits.)


omitted, for Word.


is an optional condition code (see Conditional execution).


is an optional instruction width specifier. See LDR (pc‑relative) in Thumb‑2 for details.


is the register to load or store.


is the second register to load or store.


is a program-relative expression. See Register‑relative and program‑relative expressions for more information.

label must be within a limited distance of the current instruction. See Offset range and architectures for details.


Equivalent syntaxes are available for the STR instruction in ARM code but they are deprecated.

Offset range and architectures

The assembler calculates the offset from the pc for you. The assembler generates an error if label is out of range.

Table 4.5 shows the possible offsets between label and the current instruction.

Table 4.5. pc-relative offsets

InstructionOffset rangeArchitectures
ARM LDRD+/- 255v5TE +
32-bit Thumb LDR, LDRB, LDRSB, LDRH, LDRSH [a]+/- 4095v6T2, v7
32-bit Thumb LDRD+/- 1020 [b]v6T2, v7
16-bit Thumb LDR [c]0-1020 [b]All T

[a] For word loads, Rt can be the pc. A load to the pc causes a branch to the address loaded. In ARMv4, bits[1:0] of the address loaded must be 0b00. In ARMv5T and above, bits[1:0] must not be 0b10, and if bit[0] is 1, execution continues in Thumb state, otherwise execution continues in ARM state.

[b] Must be a multiple of 4.

[c] Rt must be in the range r0-r7. There are no byte, halfword, or doubleword 16-bit instructions.


In ARMv7-M, LDRD (PC-relative) instructions must be on a word-aligned address.

LDR (pc-relative) in Thumb-2

You can use the .W width specifier to force LDR to generate a 32-bit instruction in Thumb-2 code. LDR.W always generates a 32-bit instruction, even if the target could be reached using a 16-bit LDR.

For forward references, LDR without .W always generates a 16-bit instruction in Thumb code, even if that results in failure for a target that could be reached using a 32-bit Thumb-2 LDR instruction.

Doubleword register restrictions

For Thumb-2 instructions, you must not specify sp or pc for either Rt or Rt2.

For ARM instructions:

  • Rt must be an even-numbered register

  • Rt must not be lr

  • it is strongly recommended that you do not use r12 for Rt

  • Rt2 must be R(t + 1).

Use of SP

In ARM, you can use SP for Rt in LDR word instructions. Uses of SP for Rt in LDR non-word instructions are deprecated in ARM code.

In Thumb, you can use SP for Rt in LDR word instructions only. All other uses of SP in these instructions are unpredictable in Thumb code.

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