4.1. Instruction summary

Table 4.1 gives an overview of the instructions available in the ARM, Thumb, and ThumbEE instruction sets. Use it to locate individual instructions and pseudo-instructions described in the rest of this chapter.

Note

Unless stated otherwise, ThumbEE instructions are identical to Thumb instructions.

Table 4.1. Location of instructions

MnemonicBrief descriptionPageArch. [a]
ADC, ADDAdd with Carry, AddADD, SUB, RSB, ADC, SBC, and RSCAll
ADRLoad program or register-relative address (short range)ADRAll
ADRL pseudo-instructionLoad program or register-relative address (medium range)ADRL pseudo‑instructionx6M
ANDLogical ANDAND, ORR, EOR, BIC, and ORNAll
ASRArithmetic Shift RightASR, LSL, LSR, ROR, and RRXAll
BBranchB, BL, BX, BLX, and BXJAll
BFC, BFIBit Field Clear and InsertBFC and BFIT2
BICBit ClearAND, ORR, EOR, BIC, and ORNAll
BKPTBreakpointBKPT5
BLBranch with LinkB, BL, BX, BLX, and BXJAll
BLXBranch with Link, change instruction setB, BL, BX, BLX, and BXJT
BXBranch, change instruction setB, BL, BX, BLX, and BXJT
BXJBranch, change to JazelleB, BL, BX, BLX, and BXJJ, x7M
CBZ, CBNZCompare and Branch if {Non}ZeroCBZ and CBNZT2
CDPCoprocessor Data Processing operationCDP and CDP2x6M
CDP2Coprocessor Data Processing operationCDP and CDP25, x6M
CHKACheck arrayCHKAEE
CLREXClear ExclusiveCLREXK, x6M
CLZCount leading zerosCLZ5, x6M
CMN, CMPCompare Negative, CompareCMP and CMNAll
CPSChange Processor StateCPS6
DBGDebugDBG, DMB, DSB, and ISB7
DMB, DSBData Memory Barrier, Data Synchronization BarrierDBG, DMB, DSB, and ISB7, 6M
ENTERX, LEAVEXChange state to or from ThumbEEENTERX and LEAVEXEE
EORExclusive ORAND, ORR, EOR, BIC, and ORNAll
HB, HBL, HBLP, HBPHandler Branch, branches to a specified handlerHB, HBL, HBLP, and HBPEE
ISBInstruction Synchronization BarrierDBG, DMB, DSB, and ISB7, 6M
ITIf-ThenITT2
LDCLoad CoprocessorLDC, LDC2, STC, and STC2x6M
LDC2Load CoprocessorLDC, LDC2, STC, and STC25, x6M
LDMLoad Multiple registersLDM and STMAll
LDRLoad Register with wordMemory access instructionsAll
LDR pseudo-instructionLoad Register pseudo-instructionLDR pseudo‑instructionAll
LDRBLoad Register with byteMemory access instructionsAll
LDRBTLoad Register with byte, user modeMemory access instructionsx6M
LDRDLoad Registers with two wordsMemory access instructions5E, x6M
LDREXLoad Register ExclusiveLDREX and STREX6, x6M
LDREXB, LDREXHLoad Register Exclusive Byte, HalfwordLDREX and STREXK, x6M
LDREXDLoad Register Exclusive DoublewordLDREX and STREXK, x7M
LDRHLoad Register with halfwordMemory access instructionsAll
LDRHTLoad Register with halfword, user modeMemory access instructionsT2
LDRSBLoad Register with signed byteMemory access instructionsAll
LDRSBTLoad Register with signed byte, user modeMemory access instructionsT2
LDRSHLoad Register with signed halfwordMemory access instructionsAll
LDRSHTLoad Register with signed halfword, user modeMemory access instructionsT2
LDRTLoad Register with word, user modeMemory access instructionsx6M
LSL, LSRLogical Shift Left, Logical Shift RightASR, LSL, LSR, ROR, and RRXAll
MARMove from Registers to 40-bit AccumulatorMAR and MRAXScale
MCRMove from Register to CoprocessorMCR, MCR2, MCRR, and MCRR2x6M
MCR2Move from Register to CoprocessorMCR, MCR2, MCRR, and MCRR25, x6M
MCRRMove from Registers to CoprocessorMCR, MCR2, MCRR, and MCRR25E, x6M
MCRR2Move from Registers to CoprocessorMCR, MCR2, MCRR, and MCRR26, x6M
MIA, MIAPH, MIAxyMultiply with Internal 40-bit AccumulateMIA, MIAPH, and MIAxyXScale
MLAMultiply AccumulateMUL, MLA, and MLSx6M
MLSMultiply and SubtractMUL, MLA, and MLST2
MOVMoveMOV and MVNAll
MOVTMove TopMOVTT2
MOV32 pseudo-instructionMove 32-bit constant to registerMOV32 pseudo‑instructionT2
MRAMove from 40-bit Accumulator to RegistersMAR and MRAXScale
MRCMove from Coprocessor to RegisterMRC, MRC2, MRRC and MRRC2x6M
MRC2Move from Coprocessor to RegisterMRC, MRC2, MRRC and MRRC25, x6M
MRRCMove from Coprocessor to RegistersMRC, MRC2, MRRC and MRRC25E, x6M
MRRC2Move from Coprocessor to RegistersMRC, MRC2, MRRC and MRRC26, x6M
MRSMove from PSR to registerMRSAll
MSRMove from register to PSRMSRAll
MULMultiplyMUL, MLA, and MLSAll
MVNMove NotMOV and MVNAll
NOPNo OperationNOP, SEV, WFE, WFI, and YIELDAll
ORNLogical OR NOTAND, ORR, EOR, BIC, and ORNT2
ORRLogical ORAND, ORR, EOR, BIC, and ORNAll
PKHBT, PKHTBPack HalfwordsPKHBT and PKHTB6, x7M
PLDPreload DataPLD, PLDW, and PLI5E, x6M
PLDWPreload Data with intent to WritePLD, PLDW, and PLI7MP
PLIPreload InstructionPLD, PLDW, and PLI7
PUSH, POPPUSH registers to stack, POP registers from stackPUSH and POPAll
QADD, QDADD, QDSUB, QSUBSaturating ArithmeticQADD, QSUB, QDADD, and QDSUB5E, x7M
QADD8, QADD16, QASX, QSUB8, QSUB16, QSAXParallel signed Saturating ArithmeticParallel add and subtract6, x7M
RBITReverse BitsREV, REV16, REVSH, and RBITT2
REV, REV16, REVSHReverse byte orderREV, REV16, REVSH, and RBIT6
RFEReturn From ExceptionRFET2, x7M
RORRotate Right RegisterASR, LSL, LSR, ROR, and RRXAll
RRXRotate Right with ExtendASR, LSL, LSR, ROR, and RRXx6M
RSBReverse SubtractADD, SUB, RSB, ADC, SBC, and RSCAll
RSCReverse Subtract with CarryADD, SUB, RSB, ADC, SBC, and RSCx7M
SADD8, SADD16, SASXParallel signed arithmeticParallel add and subtract6, x7M
SBCSubtract with CarryADD, SUB, RSB, ADC, SBC, and RSCAll
SBFX, UBFXSigned, Unsigned Bit Field eXtractSBFX and UBFXT2
SDIVSigned divideSDIV and UDIV7M, 7R
SELSelect bytes according to APSR GE flagsSEL6, x7M
SETENDSet Endianness for memory accessesSETEND6, x7M
SEVSet EventNOP, SEV, WFE, WFI, and YIELDK, 6M
SHADD8, SHADD16, SHASX, SHSUB8, SHSUB16, SHSAXParallel signed Halving arithmeticParallel add and subtract6, x7M
SMCSecure Monitor CallSMCZ
SMLAxySigned Multiply with Accumulate (32 <= 16 x 16  +  32)SMULxy and SMLAxy5E, x7M
SMLADDual Signed Multiply Accumulate SMLAD and SMLSD6, x7M
 (32 <= 32 + 16 x 16 + 16 x 16)  
SMLALSigned Multiply Accumulate (64 <= 64 + 32 x 32)UMULL, UMLAL, SMULL, and SMLALx6M
SMLALxySigned Multiply Accumulate (64 <= 64 + 16 x 16) SMLALxy5E, x7M
SMLALDDual Signed Multiply Accumulate LongSMLALD and SMLSLD6, x7M
 (64 <= 64 + 16 x 16 + 16 x 16)  
SMLAWySigned Multiply with Accumulate (32 <= 32 x 16  +  32)SMULWy and SMLAWy5E, x7M
SMLSDDual Signed Multiply Subtract AccumulateSMLAD and SMLSD6, x7M
 (32 <= 32 + 16 x 16 - 16 x 16)  
SMLSLDDual Signed Multiply Subtract Accumulate LongSMLALD and SMLSLD6, x7M
 (64 <= 64 + 16 x 16 - 16 x 16)  
SMMLASigned top word Multiply with Accumulate (32 <= TopWord(32 x 32  +  32))SMMUL, SMMLA, and SMMLS6, x7M
SMMLSSigned top word Multiply with Subtract (32 <= TopWord(32  -  32 x 32))SMMUL, SMMLA, and SMMLS6, x7M
SMMULSigned top word Multiply (32 <= TopWord(32 x 32))SMMUL, SMMLA, and SMMLS6, x7M
SMUAD, SMUSDDual Signed Multiply, and Add or Subtract productsSMUAD{X} and SMUSD{X}6, x7M
SMULxySigned Multiply (32 <= 16 x 16)SMULxy and SMLAxy5E, x7M
SMULLSigned Multiply (64 <= 32 x 32)UMULL, UMLAL, SMULL, and SMLALx6M
SMULWySigned Multiply (32 <= 32 x 16)SMULWy and SMLAWy5E, x7M
SRSStore Return StateSRST2, x7M
SSATSigned SaturateSSAT and USAT6, x6M
SSAT16Signed Saturate, parallel halfwordsSSAT16 and USAT166, x7M
SSUB8, SSUB16, SSAXParallel signed arithmeticParallel add and subtract6, x7M
STCStore CoprocessorLDC, LDC2, STC, and STC2x6M
STC2Store CoprocessorLDC, LDC2, STC, and STC25, x6M
STMStore Multiple registersLDM and STMAll
STRStore Register with wordMemory access instructionsAll
STRBStore Register with byteMemory access instructionsAll
STRBTStore Register with byte, user modeMemory access instructionsx6M
STRDStore Registers with two wordsMemory access instructions5E, x6M
STREXStore Register ExclusiveLDREX and STREX6, x6M
STREXB, STREXHStore Register Exclusive Byte, HalfwordLDREX and STREXK, x6M
STREXDStore Register Exclusive DoublewordLDREX and STREXK, x7M
STRHStore Register with halfwordMemory access instructionsAll
STRHTStore Register with halfword, user modeMemory access instructionsT2
STRTStore Register with word, user modeMemory access instructionsx6M
SUBSubtractADD, SUB, RSB, ADC, SBC, and RSCAll
SUBS pc, lrException return, no stackSUBS pc, lrT2, x7M
SVC (formerly SWI)SuperVisor CallSVCAll
SWP, SWPBSwap registers and memory (ARM only)SWP and SWPBAll, x7M
SXTAB, SXTAB16, SXTAHSigned extend, with AdditionSXT, SXTA, UXT, and UXTA6, x7M
SXTB, SXTHSigned extendSXT, SXTA, UXT, and UXTA6
SXTB16Signed extendSXT, SXTA, UXT, and UXTA6, x7M
TBB, TBHTable Branch Byte, HalfwordTBB and TBHT2
TEQTest EquivalenceTST and TEQx6M
TSTTestTST and TEQAll
UADD8, UADD16, UASXParallel Unsigned ArithmeticParallel add and subtract6, x7M
UDIVUnsigned divideSDIV and UDIV7M, 7R
UHADD8, UHADD16, UHASX, UHSUB8, UHSUB16, UHSAXParallel Unsigned Halving ArithmeticParallel add and subtract6, x7M
UMAALUnsigned Multiply Accumulate Accumulate LongUMAAL6, x7M
 (64 <= 32 + 32 + 32 x 32)  
UMLAL, UMULLUnsigned Multiply Accumulate, MultiplyUMULL, UMLAL, SMULL, and SMLALx6M
 (64 <= 32 x 32 + 64), (64 <= 32 x 32)  
UQADD8, UQADD16, UQASX, UQSUB8, UQSUB16, UQSAXParallel Unsigned Saturating ArithmeticParallel add and subtract6, x7M
USAD8Unsigned Sum of Absolute DifferencesUSAD8 and USADA86, x7M
USADA8Accumulate Unsigned Sum of Absolute DifferencesUSAD8 and USADA86, x7M
USATUnsigned SaturateSSAT and USAT6, x6M
USAT16Unsigned Saturate, parallel halfwordsSSAT16 and USAT166, x7M
USUB8, USUB16, USAXParallel unsigned arithmeticParallel add and subtract6, x7M
UXTAB, UXTAB16, UXTAHUnsigned extend with AdditionSXT, SXTA, UXT, and UXTA6, x7M
UXTB, UXTHUnsigned extendSXT, SXTA, UXT, and UXTA6
UXTB16Unsigned extendSXT, SXTA, UXT, and UXTA6, x7M
V*See Chapter 5 NEON and VFP Programming  
WFE, WFI, YIELDWait For Event, Wait For Interrupt, YieldNOP, SEV, WFE, WFI, and YIELDT2, 6M

[a] Entries in the Architecture column have the following meanings:

All

These instructions are available in all versions of the ARM architecture.

5

These instructions are available in the ARMv5T*, ARMv6*, and ARMv7 architectures.

5E

These instructions are available in the ARMv5TE, ARMv6*, and ARMv7 architectures.

6

These instructions are available in the ARMv6* and ARMv7 architectures.

6M

These instructions are available in the ARMv6-M and ARMv7 architectures.

x6M

These instructions are not available in the ARMv6-M profile.

7

These instructions are available in the ARMv7 architectures.

7M

These instructions are available in the ARMv7-M profile.

x7M

These instructions are not available in the ARMv6-M or ARMv7-M profile.

7R

These instructions are available in the ARMv7-R profile.

7MP

These instructions are available in the ARMv7 architectures that implement the Multiprocessing Extensions.

EE

These instructions are available in ThumbEE variants of the ARM architecture.

J

This instruction is available in the ARMv5TEJ, ARMv6*, and ARMv7 architectures.

K

These instructions are available in the ARMv6K, and ARMv7 architectures.

T

These instructions are available in ARMv4T, ARMv5T*, ARMv6*, and ARMv7 architectures.

T2

These instructions are available in the ARMv6T2 and above architectures.

XScale

These instructions are available in XScale versions of the ARM architecture.

Z

This instruction is available if Security Extensions are implemented.


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