4.3.3. SUBS pc, lr

Exception return, without stack popping.


This is a special case instruction in Thumb-2. The same instruction is available in ARM code as a normal form of the SUB instruction described in ADD, SUB, RSB, ADC, SBC, and RSC.


SUBS{cond} pc, lr, #imm



is an immediate constant. In Thumb-2 code, it is limited to the range 0-255. In ARM code, it a flexible second operand. See Flexible second operand for details.


is an optional condition code (see Conditional execution).


You can use SUBS pc, lr to return from an exception if there is no return state on the stack.

SUBS pc, lr subtracts a value from the link register and loads the pc with the result, then copies the SPSR to the CPSR.


SUBS pc, lr writes an address to the pc. The alignment of this address must be correct for the instruction set in use after the exception return:

  • For a return to ARM, the address written to the pc must be word-aligned.

  • For a return to Thumb-2, the address written to the pc must be halfword-aligned.

  • For a return to Jazelle, there are no alignment restrictions on the address written to the pc.

The results of breaking these rules are unpredictable. However, no special precautions are required in software, if the instructions are used to return after a valid exception entry mechanism.

MOVS pc, lr is a synonym of SUBS pc, lr, #0 in Thumb-2.


This ARM instruction is available in all versions of the ARM architecture.

This 32-bit Thumb instruction is available in ARMv6T2 and above, except the ARMv7-M profile.

There is no 16-bit Thumb version of this instruction.

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