RealView Compilation Tools Compiler User Guide: 4.1.2. Instruction intrinsics

4.1.2. Instruction intrinsics

The ARM compiler provides a range of instruction intrinsics for realizing ARM assembly language instructions from within your C or C++ code. Collectively, these intrinsics enable you to emulate inline assembly code using a combination of C code and instruction intrinsics.

Generic intrinsics

The Compiler Reference Guide describes the following generic intrinsics that are ARM language extensions to the ISO C and C++ standards:

See also GNU builtin functions in the Compiler Reference Guide.

Implementations of these intrinsics are available across all architectures.

Intrinsics for controlling IRQ and FIQ interrupts

The Compiler Reference Guide describes the following intrinsics that enable you to control IRQ and FIQ interrupts:

You cannot use these intrinsics to change any other CPSR bits, including the mode, state, and imprecise data abort setting. This means that the intrinsics can be used only if the processor is already in a privileged mode, because the control bits of the CPSR and SPSR cannot be changed in User mode.

These intrinsics are available for all processor architectures in both ARM and Thumb state:

If you are compiling for processors that support ARMv6 (or later), a CPS instruction is generated inline for these functions, for example:
```
    CPSID  i
```
If you are compiling for processors that support ARMv4 or ARMv5 in ARM state, the compiler inlines a sequence of MRS and MSR instructions, for example:
```
    MRS  r0, CPSR
    ORR  r0, r0, #0x80
    MSR  CPSR_c, r0
```
If you are compiling for processors that support ARMv4 or ARMv5 in Thumb state, the compiler calls a helper function, for example:
```
    BL    __ARM_disable_irq
```

For more information on these instructions, see the Assembler Guide.

Intrinsics for inserting optimization barriers

The ARM compiler can perform a range of optimizations, including re-ordering instructions and merging some operations. In some cases, such as system level programming where memory is being accessed concurrently by multiple processes, it might be necessary to disable instruction re-ordering and force memory to be updated.

The following optimization barrier intrinsics do not generate code, but they can result in slightly increased code size and additional memory accesses. In the Compiler Reference Guide, see:

Note

On some systems the memory barrier intrinsics might not be sufficient to ensure memory consistency. For example, the __memory_changed() intrinsic forces values held in registers to be written out to memory. However, if the destination for the data is held in a region that can be buffered it might wait in a write buffer. In this case you might also have to write to CP15 or use a memory barrier instruction to drain the write buffer. Refer to the Technical Reference Manual for your ARM processor for more information.

Intrinsics for inserting native instructions

The following intrinsics enable you to insert ARM processor instructions into the instruction stream generated by the compiler. In the Compiler Reference Guide, see:

Intrinsics for Digital Signal Processing

The following intrinsics described in the Compiler Reference Guide assist in the implementation of DSP algorithms:

See also ARMv6 SIMD intrinsics in the Compiler Reference Guide.

These intrinsics introduce the appropriate target instructions for:

ARM architectures from ARM v5TE onwards
Thumb-2 architectures except 'M' variants.

Not every instruction has its own intrinsic. The compiler can combine several instrinsics, or combinations of intrinsics and C operators to generate more powerful instructions. For example, the ARM5TE QDADD instruction is realized by a combination of __qadd and __qdbl.

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