| Copyright © 2002-2007 ARM Limited. All rights reserved. | ARM DUI 0207D |
| Non-Confidential | |
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| Home > ARM1136JF-S and ARM1136J-S Models > Restrictions for the ARM1136JF-S and ARM1136J-S models |
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| Home > ARM1136JF-S and ARM1136J-S Models > Restrictions for the ARM1136JF-S and ARM1136J-S models | |||
The following restrictions apply to ARM1136JF-S and ARM1136J-S models:
The caches are not modelled accurately enough to show aliasing effects for cache sizes greater than 16kB.
Under RealView Debugger the Invalidate by Range operations that are new to the ARMv6 architecture are shown as 64 bit registers. The high 32 bits of this register is the start address and the low 32 bits are the end address.
Table B.1 shows the registers that are not modeled for the ARM1136JF-S and ARM1136J-S models.
Table B.1. Registers not modeled for ARM1136JF-S and ARM1136J-S RVISS models
| Register | RealView Debugger symbol |
|---|---|
| Data Memory Remap Register | @CP15_D_MEM_REMAP |
| Instruction Memory Remap Register | @CP15_I_MEM_REMAP |
| DMA Memory Remap Register | @CP15_DMA_MEM_REMAP |
| Peripheral Port Memory Remap Register | @CP15_PERPH_MEM_REMAP |
| Instruction Cache Master Valid Register | @CP15_ICACHE_MASTER_VALID_REGISTER_0/7 |
| Instruction SmartCache Master Valid Register | @CP15_ISMARTCACHE_MASTER_VALID_REGISTER_0/7 |
| Data Cache Master Valid Register | @CP15_DCACHE_MASTER_VALID_REGISTER_0/7 |
| Data SmartCache Master Valid Register | @CP15_DSMARTCACHE_MASTER_VALID_REGISTER_0/7 |
| Main TLB VA Register | @CP15_TLB_MAIN_VA |
| Main TLB PA Register | @CP15_TLB_MAIN_PA |
| Main TLB Attribute Register | @CP15_TLB_MAIN_ATT |
| Copyright © 2002-2007 ARM Limited. All rights reserved. | ARM DUI 0207D |
| Non-Confidential | |
| PDF version | |
| Home > ARM1136JF-S and ARM1136J-S Models > Restrictions for the ARM1136JF-S and ARM1136J-S models |