RealView® ARMulator® ISS User Guide 4.10. Events

4.10. Events

RVISS has a mechanism for broadcasting and handling events. These events consist of an event number and a pair of words. The number identifies the event. The details depends on the event.

The core RVISS generates some example events, defined in armdefs.h. They are divided into the following groups:

events from the ARM processor core, listed in Table 4.3
events from the MMU and cache (not on StrongARM-110), listed in Table 4.2
events from the prefetch unit (ARM8-based processors only), listed in Table 4.4
configuration change events, listed in Table 4.6.

These events can be logged in the trace file if tracing is enabled, and trace events is turned on. Additional modules can provide new event types that are handled in the same way. User defined events must have values between UserEvent_Base (0x100000) and UserEvent_Top (0x1FFFFF).

You can catch events by installing an event handler (see Event handler). You can raise an event by calling ARMulif_RaiseEvent() (see ARMulif_RaiseEvent).

Table 4.2. Events from the MMU and cache (not on StrongARM-110)

Event name	Word 1	Word 2	Event number
`MMUEvent_DLineFetch`	Miss address	Victim address	`0x10001`
`MMUEvent_ILineFetch`	Miss address	Victim address	`0x10002`
`MMUEvent_WBStall`	Physical address of write	Number of words in write buffer	`0x10003`
`MMUEvent_DTLBWalk`	Miss address	Victim address	`0x10004`
`MMUEvent_ITLBWalk`	Miss address	Victim address	`0x10005`
`MMUEvent_LineWB`	Miss address	Victim address	`0x10006`
`MMUEvent_DCacheStall`	Address causing stall	Address fetching	`0x10007`
`MMUEvent_ICacheStall`	Address causing stall	Address fetching	`0x10008`

Table 4.3. Events from the ARM processor core

Event name	Word 1	Word 2	Event number
`CoreEvent_Reset`	-	-	`0x1`
`CoreEvent_UndefinedInstr`	pc value	Instruction	`0x2`
`CoreEvent_SVC`	pc value	SVC number	`0x3`
`CoreEvent_PrefetchAbort`	pc value	-	`0x4`
`CoreEvent_DataAbort`	pc value	Aborting address	`0x5`
`CoreEvent_AddrExceptn`	pc value	Aborting address	`0x6`
`CoreEvent_IRQ`	pc value	-	`0x7`
`CoreEvent_FIQ`	pc value	-	`0x8`
`CoreEvent_Breakpoint`	pc value	RDI_PointHandle	`0x9`
`CoreEvent_Watchpoint`	pc value	Watch address	`0xA`
`CoreEvent_IRQSpotted`	pc value	-	`0x17`
`CoreEvent_FIQSpotted`	pc value	-	`0x18`
`CoreEvent_ModeChange`	pc value	New mode	`0x19`
`CoreEvent_Dependency`	pc value	Interlock register bitmask	`0x20`

Table 4.4. Events from the prefetch unit (ARM810 only)

Event name	Word 1	Word 2	Event number
PUEvent_Full	Next pc value	-	`0x20001`
PUEvent_Mispredict	Address of branch	-	`0x20002`
PUEvent_Empty	Next pc value	-	`0x20003`

Table 4.5. Debug events

Event name	Word 1	Word 2	Event number
DebugEvent_InToDebug	-	-	`0x40001`
DebugEvent_OutOfDebug	-	-	`0x40002`
DebugEvent_DebuggerChangedPC	pc	-	`0x40003`

Table 4.6. Config events

Event name	Word 1	Word 2	Event number
ConfigEvent_AllLoaded	-	-	`0x50001`
ConfigEvent_Reset	-	-	`0x50002`
ConfigEvent_VectorsLoaded	-	-	`0x50003`
ConfigEvent_EndiannessChanged	1 (big end) or 2 (little end)	-	`0x50005`

Copyright © 2002-2007 ARM Limited. All rights reserved.	ARM DUI 0207D
Non-Confidential
PDF version