The tracer module can trace instruction execution and events from within RVISS (see Tracer). You can link your own tracing code onto the tracer module.

Not supported by RealView Debugger. However, you can use RealView Debugger tracing to capture profiling information.

See the RealView Debugger Trace User Guide for more details.

On reset, this module sets up cache, MPU or MMU and associated pagetables inside RVISS (see Pagetable module).

This model does nothing. You can use this in the peripherals.ami file to disable models (see Configuring RVISS to disable a model).

This model provides the semihosting SVCs described in RealView Compilation Tools Libraries and Floating Point Support Guide.

This is a model of a Debug Communications Channel (DCC).

This model enables you to specify the characteristics of a memory system. See Map files for more information.

flatmem models a zero-wait state memory system. See Default memory model for more information.

validate is a coprocessor model used for validation with some cores. It can generate delayed IRQ and FIQ signals, for example.

See Interrupt controller. intc is a model of the interrupt controller peripheral described in the Reference Peripherals Specification (RPS).

See Timer. timer is a model of the RPS timer peripheral. Two timers are provided. timer must be used in conjunction with an interrupt controller, but not necessarily intc.

A simple millisecond timer.

Watchdog. See Watchdog. watchdog is a generic watchdog model. It does not model any specific watchdog hardware, but provides generic watchdog functions.

Tube. See Tube. tube is a simple debugging aid. It enables you to check that writes are taking place to a specified location in memory.