is the value of interf->handle set in MemInit.

is the value on the address bus.

is a pointer to the data for the memory access. See Data for reads and writes for details.

encodes the type of cycle. On some processors, for example, cached processors, some of the signals are not valid. See Macros for access types for details of the macros for determining access type.

Indicates successful completion of the cycle.

Tells the processor to busy-wait and try the access again next cycle.

Signals an abort.

Signals successful return of a single word of a doubleword load. To load the second word, the caller increments address by 4 and issues a single word load.