RealView® ARMulator® ISS User Guide

Version 1.4.3


Table of Contents

Preface
About this book
Intended audience
Using this book
Typographical conventions
Further reading
Feedback
Feedback on RealView ARMulator ISS
Feedback on this book
1. Introduction
1.1. RealView ARMulator ISS overview
1.1.1. What is RealView ARMulator ISS?
1.1.2. Semihosting
2. RVISS Basics
2.1. About RVISS
2.1.1. Accuracy
2.2. Connections to RVISS in RealView Debugger
2.2.1. RealView Debugger features supported for RVISS connections
2.3. RVISS components
2.3.1. Configuring RVISS
2.4. Tracer
2.4.1. RealView Debugger support for tracing
2.4.2. Enabling the RVISS Tracer feature in RealView Debugger
2.4.3. Configuring Tracer
2.4.4. Interpreting trace file output
2.5. RVISS cycle types
2.5.1. Uncached von Neumann cores
2.5.2. Uncached Harvard cores
2.5.3. Cached cores with MMUs or MPUs and AMBA ASB interfaces
2.5.4. Cached cores with MMUs or MPUs and AMBA AHB interfaces
2.5.5. Internal cycle types for cached cores
2.5.6. StrongARM1
2.5.7. Core-specific verbose statistics
2.5.8. See also
2.6. Pagetable module
2.6.1. Overview of the pagetable module
2.6.2. Controlling the MMU, MPU or MPU and cache
2.6.3. Controlling registers 2 and 3
2.6.4. Memory regions
2.6.5. Pagetable module and memory management units
2.6.6. Pagetable module and memory protection units
2.7. Default memory model
2.8. Memory modeling with mapfiles
2.8.1. Overview of memory modeling with mapfiles
2.8.2. Clock frequency
2.8.3. Selecting the mapfile memory model
2.8.4. How the mapfile memory model calculates wait states
2.8.5. Configuring the map memory model
2.9. Semihosting
2.9.1. Semihosting configuration
2.10. Peripheral models
2.10.1. Configuring RVISS to use the peripheral models
2.10.2. Configuring details of the peripherals
2.10.3. Interrupt controller
2.10.4. Timer
2.10.5. Watchdog
2.10.6. Tube
3. Writing RVISS Models
3.1. The RVISS extension kit
3.1.1. Location of files
3.1.2. Supplied models
3.2. Writing a new peripheral model
3.2.1. Using a sample model as a template
3.2.2. Return values
3.2.3. Initialization, finalization, and state macros
3.2.4. Registering your model
3.3. Building a new model
3.3.1. How to build a new model
3.4. Configuring RVISS to use a new model
3.4.1. Adding a .dsc file
3.4.2. Editing default.ami and peripherals.ami
3.5. Configuring RVISS to disable a model
4. RVISS Reference
4.1. SimRdi_Manager interface
4.1.1. Using the SimRdi_Manager interface
4.1.2. Header files
4.1.3. Supported SimRdi_Manager services
4.1.4. Adding a SimRdi_Manager listener
4.1.5. Version information
4.1.6. Advertising the SimRdi_Manager services provided by your model
4.1.7. Global break service
4.1.8. Register services
4.1.9. Register windows service (regwin)
4.1.10. Other members of SimRdiProcVec
4.1.11. Stopping RVISS
4.2. RVISS models
4.2.1. Configuring models through ToolConf
4.3. RVISS model insertion
4.3.1. Example 1: RVISS without the Mapfile and Tracer inserted
4.3.2. Example 2: RVISS with Mapfile inserted, and Tracer inserted in one link
4.3.3. Example 3: RVISS with Mapfile inserted, and Tracer inserted in two links
4.4. Communicating with the core
4.4.1. Mode numbers
4.4.2. ARMulif_GetReg
4.4.3. ARMulif_SetReg
4.4.4. ARMulif_GetPC and ARMulif_GetR15
4.4.5. ARMulif_SetPC and ARMulif_SetR15
4.4.6. ARMulif_GetCPSR
4.4.7. ARMulif_SetCPSR
4.4.8. ARMulif_GetSPSR
4.4.9. ARMulif_SetSPSR
4.4.10. ARMulif_ThumbBit
4.4.11. ARMulif_GetMode
4.4.12. ARMulif_CPRead
4.4.13. ARMulif_CPWrite
4.4.14. ARMulif_SetConfig
4.5. Basic model interface
4.5.1. Declaration of a private state data structure
4.5.2. Model initialization
4.5.3. Model finalization
4.6. The memory interface
4.6.1. Memory type variants
4.7. Memory model interface
4.7.1. Memory model initialization function
4.7.2. armul_ReadClock
4.7.3. armul_GetCycleLength
4.7.4. armul_ReadCycles
4.7.5. armul_MemAccess
4.7.6. armul_MemAccess2
4.7.7. armul_MemAccAsync
4.7.8. armul_HarvardMemAccess
4.7.9. Data for reads and writes
4.7.10. Macros for access types
4.8. Coprocessor model interface
4.8.1. ARMulif_InstallCoprocessorV5
4.8.2. LDC
4.8.3. STC
4.8.4. MRC
4.8.5. MCR
4.8.6. MCRR
4.8.7. MRRC
4.8.8. CDP
4.8.9. read
4.8.10. write
4.9. Exceptions
4.9.1. ARMulif_SetSignal
4.9.2. ARMulif_GetProperty
4.10. Events
4.10.1. ARMulif_RaiseEvent
4.11. Handlers
4.11.1. Exception handler
4.11.2. Unknown information handler
4.11.3. Event handler
4.12. Memory access functions
4.12.1. Reading from a given address
4.12.2. Writing to a specified address
4.13. Event scheduling functions
4.13.1. ARMulif_ScheduleTimedFunction
4.13.2. ARMulif_DescheduleTimedFunction
4.14. General purpose functions
4.14.1. ARMul_AddCounterDesc
4.14.2. ARMul_AddCounterValue
4.14.3. ARMul_AddCounterValue64
4.14.4. ARMul_BusRegisterPeripFunc
4.14.5. ARMulif_CoreCycles
4.14.6. ARMulif_CPUCycles
4.14.7. ARMulif_EndCondition
4.14.8. ARMulif_GetCoreClockFreq
4.14.9. ARMulif_InstallHourglass
4.14.10. ARMulif_ReadBusRange
4.14.11. ARMulif_RemoveHourglass
4.14.12. ARMulif_StopExecution
4.14.13. ARMulif_Time
4.14.14. Hostif_RaiseError
4.15. Accessing the RealView Debugger
4.15.1. Hostif_ConsolePrint
4.15.2. Hostif_ConsoleRead
4.15.3. Hostif_ConsoleReadC
4.15.4. Hostif_ConsoleWrite
4.15.5. Hostif_DebugPause
4.15.6. Hostif_DebugPrint
4.15.7. Hostif_PrettyPrint
4.15.8. Hostif_WriteC
4.16. Tracer
4.16.1. Tracer_Open
4.16.2. Tracer_Dispatch
4.16.3. Tracer_Close
4.16.4. Tracer_Flush
4.17. Map files
4.17.1. Format of a map file
4.18. RVISS configuration files
4.18.1. Predefined tags
4.18.2. Processors
4.18.3. Adding a variant processor model
4.18.4. Changing the cache or TCM size of a synthesizable processor
4.19. ToolConf
4.19.1. Toolconf overview
4.19.2. File format
4.19.3. Boolean flags in a ToolConf database
4.19.4. SI units in a ToolConf database
4.19.5. ToolConf_Lookup
4.19.6. ToolConf_Cmp
4.20. Reference peripherals
4.20.1. Interrupt controller
4.20.2. Timer
A. Using MPCore Models
A.1. About MPCore
A.2. Default peripheral system
A.3. Limitations
A.4. Writing a new MPCore model
A.4.1. Interrupts
A.4.2. Configuring your new model
A.4.3. Setting up your new model
B. ARM1136JF-S and ARM1136J-S Models
B.1. Restrictions for the ARM1136JF-S and ARM1136J-S models

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks owned by ARM Limited. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision AAugust 2002Release 1.3
Revision BNot Released
Revision CJanuary 2004Release 1.4 for RVDS v2.1
Revision DMarch 2007Release 1.4.3 for RVDS v3.1
Copyright © 2002-2007 ARM Limited. All rights reserved.ARM DUI 0207D
Non-Confidential