3.6. Clock architecture

The IM-LT3 generates four clocks and has three connections to the SYSCLK signals from an attached Integrator/CP baseboard (if used) and up to seven clocks from attached tiles.

The local programmable clocks are supplied by three clock generator chips. Their frequencies are selected in oscillator control registers within the FPGA. A 24MHz reference clock is supplied to the clock generators, FPGA, and PLD.

For information on Logic Tile clocking schemes, see the Integrator/XC2V4000+ Logic Tile User Guide. For information on Core Module or baseboard clocking, see the documentation supplied with the product. Additional information on clocking systems might be present in the application note for the specific combination of boards.

Figure 3.7 and Figure 3.7 show the architecture of the clock system.

Figure 3.7. Clock signal routing (Core Module)

Figure 3.8. Clock signal routing (Core Tile)

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