3.9. Switches and LEDs

Figure 3.23 shows a block diagram of the switch and LED circuit.

Figure 3.23. Switch and LED block diagram

Figure 3.24 shows the switch and LED locations.

Figure 3.24. Switch and LED location

There are two pushbuttons and three switch banks fitted to the IM-LT3:

S1[8:1]

These switches are connected to YU[143:136] and can be read under program control from a register implemented in an attached Logic Tile. (Switch S1[1] is connected to signal YU[136].) If a switch is on, a logic HIGH signal is produced.

S2

This pushbutton switch pulls nPB1 LOW and the FPGA resets the system.

S3[4:1]

These switches (signals SW[3:0]) are connected to the FPGA. Switch S3[1] is signal SW[0]. If a switch is on, a logic HIGH signal is produced.

S4[2:1]

These switches (signals SEL[2:1]) select the image to load into the FPGA at power on (see Configuring the FPGA from flash).

S5

This switch triggers (CFG_nPROG) reloads the selected configuration image from flash to the FPGA.

There two banks of eight user LEDs and four individual status LEDs:

3V3

LED D19 lights to indicate that 3.3V is connected to the module.

DONE

LED D20 lights to indicate that FPGA configuration has completed.

CONFIG

LED D25 lights to indicate that the CONFIG link is connected and the system is in configuration mode.

FPGA IMAGE

LED D21lights to indicate that image 1 in the top half of the flash memory is loaded into the FPGA. If unlit, image 0 is loaded into the FPGA.

FPGA LEDs

LEDs D11 to D18 are connected to the IM-LT3 FPGA (signals R_LEDS[7:0]).

A HIGH level lights the LED. (LED D11 is signal R_LEDS[0].)

Logic Tile LEDs

LEDs D1 to D8 are connected to YU[135:128] and can be lit by an attached Logic Tile.

A HIGH level lights the LED. (LED D1 is connected to YU[128].)

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