3.6.2. ICS307 clock generators

The ICS307s references are supplied by a 24MHz crystal. The frequency of the outputs from the ICS307s are controlled by values loaded into the serial data pins. This enables them to produce a wide range of frequencies.

The IM-LT3 produces the fixed-frequency 24MHz clocks REF24MHZ (clock input to the FPGA) and PLD_REF24MHZ (clock input to PLD).

For more information on the ICS307, see the manufacturer’s data sheet.

Programmable clocks on the IM-LT3

The IM-LT3 provides the programmable clock sources R_CLK[2:0].

These clocks are supplied by three MicroClock ICS307 clock generators, as shown in Figure 3.9.

Figure 3.9. Programmable clock generators

Programming the ICS307 clocks

The frequency of clocks from an ICS307 is set by loading values for the divider and multiplier registers into the serial input port on the clock generator. These control the value of three parameters used to determine the output of the ICS307. Calculate the frequency using the formula:

R_CLKfreq = 48 * ((VDW+ 8) / ((RDW+2)*OD))

where:

VDW

Is the VCO divider word (4 to 511).

RDW

Is the reference divider word (1 to 127).

OD

Is the output divider. The divider code for each bit combination is shown in Table 3.5.

Table 3.5. Output Divider code

S2S1S0Divider ratio
00010
0012
0108
0114
1005
1017
1103
1116

The configuration data stream is shown in Figure 3.10 where:

C[1:0]

Internal load capacitance for crystal. If an external clock is used, set C[1:0] to 10.

T

Duty cycle threshold setting:

  • 0 selects 1.4V as duty-cycle reference point

  • 1 selects VDD/2 as duty-cycle reference point.

F[1:0]

Function of CLK2 output:

  • 00 selects reference signal

  • 01 selects reference signal divided by two

  • 10 disables output for CLK2

  • 11 selects CLK1 signal divided by two.

S[2:0]

Output divider select (OD)

V[8:0]

VCO divider word (VDW)

R[6:0]

Reference divider word (RDW).

Figure 3.10. VCO configuration data

Note

Bit 23 is loaded into the shift register first and bit 0 is loaded last. Data is clocked into the register on the rising edge of SCLK. The STROBE signal is pulsed high after all bits have been shifted into the register.

See the application notes for the IM-LT3 for details of implementing the clock interface logic in the FPGA.

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