3.4. Reset control

Figure 3.3 shows the architecture of the reset circuitry. The PLD incorporates a reset controller that enables the Core Module to be reset as a standalone unit or as part of an Integrator development system. The system can be reset from by:

Table 3.3 describes the external reset signals.

Table 3.3. Reset signal descriptions

Signal

Description

Type

Function

nPB

User pushbutton

Local

For Integrator/CP systems, a reset signal is generated by the FPGA from the nPB signal from pushbutton switch S2.

nSRST

System reset

Bidirectional

The nSRST open collector output signal is driven LOW by the module FPGA when the signal PBRST or software reset (SWRST) is asserted.

As an input, nSRST can be driven LOW by the JTAG interface box.

nSYSRST

System reset

Bidirectional

nSYSRST can be driven by an FPGA on any attached board. Typically this will be driven by the master system reset controller such as a motherboard.

The nSYSRST signal is used by Core Modules.

nSYSPOR

System reset

Output

The nSYSPOR signal is generated by an RC delay on GLOBAL_DONE. The reset is held active LOW until GLOBAL_DONE goes HIGH. nSYSPOR is used by external modules or tiles as a general reset signal.

nPORESET

System reset

Local

The nPORESET signal goes HIGH 7μS after 3.3V is supplied by the supply voltage. The reset drives the nTRST signal LOW.

CFGnPROG

Image reload

Local

The CFGnPROG signal goes LOW to initiate the loading of the FPGA image from the configuration flash. The signal can be triggered by the RECONFIG pushbutton S5 or by an external reset.

GLOBAL_DONE

System FPGAs configured

Bidirectional

This signal is driven low until CFG_DONE is HIGH. Other boards in the system pull this signal LOW if the local configuration sequence has not finished. There is a delay between CFG_DONE and GLOBAL_DONE to allow serial communication and configuration of the PLD.

CFG_DONE

System FPGAs configured

Local

The FPGA will drive this signal high following a successfully image configuration.

CFG_nWRITE

FPGA and PLD configuration

Local

CFG_nWRITE is an input to the FPGA that initiates sending the serial stream to the PLD. The PLD drives CFG_nWRITE HIGH 16 CCLK cycles (64 cycles of the 24MHz clock) after CFG_DONE goes HIGH. After the FPGA finishes sending the serial stream to the PLD, the PLD releases GLOBAL_DONE.

Note

See the documentation for the other board products for more information on reset.

Figure 3.3. Reset control

The general purpose pushbutton S2 generates the nPB signal to the FPGA. For the Integrator/CP FPGA image, this signal triggers a reset of the board stack.

Figure 3.4 shows the reset timing.

Figure 3.4. Reset sequence timing

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