3.7.1. SDRAM interface

A socket for a single SDRAM DIMM is provided. The signals from the socket go to the FPGA and an SDRAM controller can be implemented in the FPGA.

Serial presence detect

JEDEC-compliant SDRAM DIMMs incorporate a Serial Presence Detect (SPD) feature. This comprises a 2048-bit serial EEPROM located on the DIMM with the first 128 bytes programmed by the DIMM manufacturer to identify the following:

  • tile type

  • memory organization

  • timing parameters.

The EEPROM clock (SCL) operates at 93.75kHz (24MHz divided by 256). The transfer rate for read accesses to the EEPROM is 100kbit/s maximum. The data is read out serially 8 bits at a time, preceded by a start bit and followed by a stop bit. This makes reading the EEPROM a very slow process and it takes approximately 27ms to read all 256 bytes.

Write accesses to the SPD EEPROM are not supported.

SDRAM signals

The distribution of clock and control signals to the DIMM socket is shown in Figure 3.11.

Figure 3.11. SDRAM clock and control signals

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