C.5. Register and memory overview

Table C.5 shows a map for a typical Integrator/CP system. See the Integrator/CP User Guide for more details on register function.

Note

The memory map below 0x10000000 depends on the settings for TCM enabled and REMAP.

Table C.5. System control register map

Peripheral or deviceAddress rangeSize

Boot flash. Mapped at this address only at power ON, and then disabled to allow access to SSRAM.

0x000000000x000FFFFF1MB
SDRAM0x001000000x0FFFFFFF255MB
Control registers0x10000000–0x1000003F64 bytes

Interrupt controller

Note

The Integrator/CP are described in Interrupt control.

0x100000400x1000007F64 bytes

Reserved

Note

The CT7TDMI, CT926EJ-S, and CT1136JF-S use 0x100000800x10000008C and 0x100000A00x1000000AC as voltage control registers.

The CT926EJ-S also uses 0x10000094 for Core Tile PLD configuration.

Refer to the documentation supplied with the Core Tiles for details.

0x100000800x100000FF128 bytes
Serial Presence Detect memory0x100001000x100001FF256 bytes
Counter/timers0x130000000x13FFFFFF16MB
Primary interrupt controller registers0x140000000x14FFFFFF16MB
Real time clock0x150000000x15FFFFFF16MB
UART00x160000000x16FFFFFF16MB
UART10x170000000x17FFFFFF16MB
Keyboard0x180000000x18FFFFFF16MB
Mouse0x190000000x19FFFFFF16MB
Debug LEDs and DIP switch0x1A0000000x1AFFFFFF16MB
Reserved0x1B0000000x1BFFFFFF16MB
Multimedia Card Interface0x1C0000000x1CFFFFFF16MB
Advanced Audio CODEC Interface0x1D0000000x1DFFFFFF16MB
Touch Screen Controller Interface0x1E0000000x1EFFFFFF16MB
Reserved0x1F0000000x1FFFFFFF16MB
Flash (size depends on board device)0x200000000x27FFFFFF148MB
Reserved0x280000000xBFFFFFFF2416MB
CLCD regs/palette0xC00000000xC0FFFFFF16MB
Reserved0xC10000000xC7FFFFFF112MB
Ethernet0xC80000000xC8FFFFFF16MB
GPIO0xC90000000xC9FFFFFF16MB
Secondary interrupt controller0xCA0000000xCAFFFFFF16MB
CP control registers0xCB0000000xCBFFFFFF16MB
Reserved0xCC0000000xFFFFFFFF832MB

Note

Device registers are usually mapped repeatedly to fill their assigned spaces. However, to ensure correct operation on future product versions, it is advisable to only access the register at its true address.

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