Integrator™/IM-LT3 User Guide C.5.1. CM control registers for Integrator/CP

C.5.1. CM control registers for Integrator/CP

Table C.6 lists the CM register that are typically present on a Core Module. These registers are also implemented on the IM-LT3 when stacked on Integrator/CP. Refer to the Core Module documentation supplied on the CD provided with your IM-LT3 for more details on Core Module registers.

Note

Some registers might not function as expected on the IM-LT3 and Core Tile combination (CM_ID for example).

The CM_CTRL register is modified in the FPGA image used for the IM-LT3 on an Integrator/CP (see Core Module control register, CM_CTRL).

Table C.6. Core Module status, control, and interrupt registers

Register Name	Address	Description
CM_ID	`0x10000000`	Core Module identification register
CM_PROC	`0x10000004`	Core Module processor register
CM_OSC	`0x10000008`	Core Module oscillator register
CM_CTRL	`0x1000000C`	Core Module control
CM_STAT	`0x10000010`	Core Module status
CM_LOCK	`0x10000014`	Core Module lock
CM_LMBUSCNT	`0x10000018`	Core Module local memory bus cycle counter
CM_AUXOSC	`0x1000001C`	Core Module auxiliary clock oscillator register
CM_SDRAM	`0x10000020`	SDRAM status and control register
CM_INIT	`0x10000024`	Core Module initialization register
CM_REFCT	`0x10000028`	Reference clock cycle counter
-	`0x1000002C`	Reserved
CM_xFLAGx	`0x10000030`–`0x1000003C`	Core Module flag registers

Core Module control register, CM_CTRL

The Core Module and LCD control register (CM_CTRL) at 0x1000000C is a read/write register that controls user-configurable features of the IM-LT3 and the display interface on the Integrator/CP baseboard. Refer to the Core Module documentation supplied on the CD provided with your IM-LT3 for more details on Core Module registers.

Figure C.8. CM_CTRL

Table C.7 and Figure C.8 describe the Core Module control register bits

Table C.7. CM_CTRL register

Bits	Name	Access	Function
[31:21]	Reserved	Use read-modify-write to preserve value.
[20]	EBI_WP	Write	This bit controls the write power signal to the Core Module user flash in EBI[1] and EBI[2]. 0 = flash write protected 1= flash can be written to.
[19]	n24BITEN	Write	Select VGA depth: 0 = 24bit VGA 1 = 18bit VGA Must be 1 to enable BIAS control.
[18]	STATIC	Write	No connection on Sharp panel.
[17]	STATIC2	Write	Up/down axis flip on Sharp panel.
[16]	STATIC1	Write	Right/left axis flip on Sharp panel.
[15]	Enable LCD1	Write	Enable, active high.
[14]	Enable LCD0	Write	Enable, active high
[13:11]	LCDMUXSEL	Write	001 = Generic LCD connector, 24-bit mode 011 = Sharp LCD panel 100 = Sharp LCD panel 111 = 24-bit VGA
[10]	LCDBIASDN	Write	Low to high transition decreases LCD bias voltage (dimmer)
[9]	LCDBIASUP	Write	Low to high transition increases LCD bias voltage (brighter)
[8]	LCDBIASEN	Read/write	Enable LCD bias supply
[7:4]	Reserved	Use read-modify-write to preserve value.
[3]	RESET	Write	This is used to reset the Core Tile, Integrator/CP, and IM-LT3. A reset is triggered by writing a 1. Reading this bit always returns a 0 allowing you to use read-modify-write operations without masking the RESET bit.
[2]	REMAP	Read/write	This bit is used to control REMAP: 0 = flash at address 0 1= SRAM at address 0.
[1]	nMBDET	Read	This bit indicates whether or not the IM-LT3 is mounted on a CP baseboard: 0 = mounted on baseboard 1 = no baseboard
[0]	LED	Read/write	This bit controls LED0 on the IM-LT3: 0 = LED OFF 1 = LED ON.

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