C.3. Top level memory map

Figure C.4 shows the top-level memory map of an Integrator/CP system. The memory map maintains compatibility with other platforms in the Integrator product family.

Figure C.4. Top-level memory map

The memory map contains areas for the SSRAM, SDRAM, flash memory, and peripherals. It also contains an area reserved for expansion at 0xD00000000xFFFFFFFF.


The processor cores on different boards might have different amounts of cache and TCM. The size of the cache and TCM on a board can be identified by reading registers in CP15.

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