A.7. Integrated logic analyzer connector signals

Figure A.6 shows the signals on the integrated logic analyzer connector J12. Use an embedded logic analyzer to debug FPGA designs and software (running on a physical or synthesized ARM core) at the same time. The ILA signals use a separate JTAG path to the FPGA and remain functional even if the system is in debug mode. For more information, see the documentation supplied with your analyzer. (The ChipScope product is described on the Xilinx web site at www.xilinx.com.)

Figure A.6. Embedded logic analyzer connector J33


Pins 4,6, and 10 have 10kΩ pullups to 3.3V to maintain the signals at an inactive level unless an analyzer is connected.

Connector J12 uses a 2mm pitch connector. The Xilinx JTAG cable is compatible with this connector. Use a flying probe or make an adaptor cable if a different JTAG interface is used. Using a different JTAG cable and interface might require a reduction in the JTAG clock speed (to 1MHz for example).

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