3.8.4. JTAG scan paths

This section describes JTAG scan chain data, clock, and TMS paths.

The JTAG chain on the IM-LT3 is split into two chains that are connected to the tiles as:


The debug JTAG signals are used with a processor core (implemented as an SMM in FPGAs or an external Core Module or Core Tile).

In this mode, the JTAG signals are not routed to the configuration inputs. The signals from the ILA (Chip Scope) connector, however, can provide some configuration control even while the JTAG signals are being used for debugging.


The configuration JTAG signals are used to load the configuration flash for the FPGA or to reprogram the PLD.

Data path

Figure 3.15 and Figure 3.16 show the data path. The switches are in debug (user) mode.

Figure 3.15. JTAG data path block diagram (Core Module)

Figure 3.16. JTAG data path block diagram (Core Tile)

When you use the IM-LT3 and a tile as a standalone development system, the data path is routed to the tile and back to the JTAG connector.

Figure 3.17 and Figure 3.18 show a simplified diagram of the JTAG data path in debug mode.

If the IM-LT3 and tile is attached to an Integrator baseboard, the TDI signal from the JTAG connector is routed down through the HDRB connectors to the baseboard. From there the path is routed back up the stack through each tile, before being returned to the JTAG connector as TDO.

The motherboard detect signal nMBDET controls a switching circuit on the IM-LT3 and tile and, therefore, the routing of TDI.

In configuration mode, the PLDs and FPGAs are included in the scan chain as described in JTAG connection modes. In debug mode however, the JTAG signals are simply routed through the FPGA and the FPGA is not visible in the scan path. (The FPGA will be visible, however, if the re is a user-implemented TAP controller in the FPGA).

Figure 3.17. Simplified view of data path in debug mode (Core Module)

Figure 3.18. Simplified view of data path in debug mode (Core Tile)

Clock path

The clock path is routed in a similar way to the data path, although in the opposite direction. Figure 3.19 and Figure 3.20 show a simplified diagram of the clock path. The position for the TILE_RTC switch is for user mode (the CONFIG jumper is not fitted).

A number of synthesized cores sample TCK. This introduces a delay into the clock path. Cores of this type pass on the delayed clock signal as RTCK, which is fed to the TCK input of the next device in the chain. The RTCK signal at the JTAG connector is regulates the advance of TCK (see the ARM Multi-ICE User Guide).

The routing of the TCK/RTCK signals through the stack is controlled by switches in a similar way to the data path. The routing of RTCK is controlled by the signal nRTCKEN and an AND gate on the motherboard. See the Integrator/XC2V4000+ User Guide for details on control of nRTCKEN. If a Core Module is used without a motherboard fitted beneath it, fit the stacking option link on the Core Module to cause the RTCK signal to be routed back to the upper header connector (see the schematic for the Core Module for the link settings).

Figure 3.19. JTAG clock path (Core Module)

When the IM-LT3 is being used to support an ARM core in an adjacent Core Tile, the PLD can be set to assert the nRTCKEN signal. This is done via the PLD serial configuration stream that is described in PLD circuitry.

Figure 3.20. JTAG clock path (Core Tile)

TMS path

Figure 3.21 and Figure 3.22 show the TMS path. The switch positions are for user mode (the CONFIG jumper is not fitted).

Figure 3.21. TMS path (Core Module)

Figure 3.22. TMS path (Core Tile)

Copyright © 2005, 2006 ARM Limited. All rights reserved.ARM DUI 0216B