3.5.1. Voltage on header pins

The voltages on the lower Integrator/CP-style connectors are the same as those on the Integrator/CM family of Core Modules. The logic signals on the lower header are standard Integrator/CM logic levels (3.3V).

The voltages on the upper connectors depends on the connector and on configuration settings:

Figure 3.5 shows the voltages present on the HDRX, HDRY, and HRDZ tile connectors.

Figure 3.5. Voltages present on tile connector blades

Relationship between voltage supply and signal levels

Because of the configurable tile voltage and the types of logic used on the expansion tiles, there are different signal levels present on the connectors:

  • All HDRA and HDRB signal pins are at 3.3V logic levels.

  • HDRY odd pins 45 to 107 (the F bus) always use 3.3V logic levels if HDRB is connected to an Integrator system.

    All other HDRY signals are connected to the FPGA and are set by the VDDIO_Y level from the tile above. VDDIO_Y is connected to 3.3V by a MOSFET transistor if no tile is present. VDDIO_Y can be manually connected to 3.3V by fitting resistor links R112 and R113 on the PCB, but normally it is supplied only by the tile above.

  • HDRX signals are connected to the FPGA and are set by the VDDIO_X level from the tile above. VDDIO_X is connected to 3.3V by a MOSFET transistor if no tile is present. VDDIO_X can be manually connected to 3.3V by fitting resistor links R133 and R134 on the PCB, but normally it is supplied only by the tile above.

    Note

    If the SSRAM on the IM-LT3 is used, some of the HDRX signals must match the signal level used for the SSRAM.

  • All HDRZ signals operate at a 3.3V logic level.

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