1.2.5. Test and debug interfaces

The IM-LT3 has connectors that enable configuration and monitoring of the board:

JTAG connector

The JTAG connector enables JTAG equipment, such as Multi-ICE or RealView ICE, to be connected to the IM-LT3. The JTAG signals are routed to all tiles stacked on the IM-LT3 and enable configuration of all programmable logic and onboard flash memory. See JTAG support.

Always use the JTAG connector on the IM-LT3 Interface Module.

Trace and logic analyzer connectors

There are two Mictor logic analyzer connectors on the IM-LT3 that are used for general-purpose debug. If an Soft Macrocell Model (SMM) core is implemented in the FPGA on an attached Logic Tile however, one connector can be configured as a trace port (up to 16-bits wide) and the trace signals from the ETM can be monitored by a Trace Port Analyzer. (See Mictor logic analyzer connectors.)

Each Core Tile has trace connectors for the test chip on the board. In some stacking configurations, a right-angle adapter cable is required for connecting a trace unit to the trace port connectors.

Integrated Logic Analyzer connector

The IM-LT3 also has an Integrated Logic Analyzer (ILA) connector that can be used with Xilinx ChipScope analyzer. This connector provides access to the JTAG configuration chain when the normal JTAG chain is in debug mode.

The IM-LT3 also has LEDs and switches that can be used to configure or test images implemented in the IM-LT3 or Logic Tile FPGAs:


There are eight LEDs that can be lit by the IM-LT3 FPGA and eight LEDs that can be lit by FPGA signals from an attached Logic Tile.


There are four user switches that are connected to the IM-LT3 FPGA nd eight switches that can are connected to the FPGA in an attached Logic Tile.

Two image selector switches enable different FPGA images to be loaded at reset. This is useful when testing a new design.

The general purpose pushbutton S2 generates the nPB signal to the FPGA. For the Integrator/CP FPGA image, this signal triggers a reset of the board stack.

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