1.3. Typical configurations

Typical configurations for the IM-LT3 are listed in Table 1.1. For all configurations, a Versatile/IT1 Interface Tile or Versatile/AT1 Analyzer Tile can be used to provide access to signals on the tile header connectors.

Table 1.1. Typical configurations

Baseboard optionCore ModuleLogic TileCore TileDescription
No baseboardNo0-3NoStandalone SMM system. The Logic TIle FPGAs are loaded with a Soft Macrocell Model (SMM) implementation of a processor and is used to test processor designs. The IM-LT3 FPGA contains a design that provides control functions and enables the SMM to access the SDRAM on the IM-LT3.
No baseboard 10-2NoA single-processor standalone system based on a Core Module. The optional Logic Tiles contain peripheral implementations
No baseboardNo0-21A single-processor standalone system based on a Core Tile.
No baseboard0 or 10-21 or 2A multi-processor standalone system based on Core Tiles. If more than one Core Tile is used, each Core Tile must be separated by a Logic Tile.
No baseboard1-30-20, 1 or 2A multi-processor standalone system based on Core Modules. If more than one Core Tile is used, each Core Tile must be separated by a Logic Tile.
Integrator/CPNo0-3NoExpanded SMM system. The Logic Tile FPGAs are loaded with an SMM. The IM-LT3 FPGA contains a design that enables the SMM to access the SDRAM on the IM-LT3 and the peripherals on the baseboard.
Integrator/CP10-2NoA single processor system with the Integrator/CP providing I/O. The IM-LT3 and optional Logic Tiles contain peripheral implementations
Integrator/CPNo0-21A single processor system with the Integrator/CP providing I/O. The optional Logic Tiles contain peripheral implementations

Note

See the applications notes provided on the CD and on the ARM web site for more details of stacking options and FPGA images. Not all board combinations have an FPGA image supplied.

The maximum number of Core Modules, Logic Tiles, and Core Tiles is limited by the power supply.

Figure 1.3 shows an Integrator/CP system consisting of an Integrator/CP, an IM-LT3, and a Core Tile.

Figure 1.3. Integrator/CP system

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