C.4.3. HDL files

The IM-LT3 image provides the CP functional blocks as a set of HDL files. These are described in Table C.4.

Table C.4. IM-LT3 FPGA image functional FPGA block HDL file descriptions



The decoder block provides the high-speed peripherals with select lines. The decoder blocks also contain the default slave peripheral to simplify the example structure. The Integrator family of boards uses a distributed address decoding system.


This is the AHB multiplexor that connects the read data buses from all of the slaves to the AHB master(s).


This is the bridge block required to connect APB peripherals to the high-speed AMBA AHB bus. It produces the peripheral select signals for each of the APB peripherals.


The APB register peripheral provides memory-mapped registers that you can use to:

  • configure the two clock generators (protected by the LM_LOCK register)

  • write to the user LEDs

  • read the user switch inputs.


The APB interrupt controller contains all of the standard interrupt controller registers and has an input port for four APB interrupts. (The example only uses one of them. The remaining three are set inactive in the AHBAPBSys block.) Four software interrupts are implemented.

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