C.8.1. Interrupt controllers

Integrator/CP system interrupts are generated by the Primary Interrupt Controller (PIC), the Secondary Interrupt Controller (SIC), and the Communications Interrupt Controller (CIC).

Detecting and clearing interrupts requires that each interrupt controller be correctly initialized as well as the interrupt control register in the individual peripheral.

Primary interrupt controller

The PIC is implemented within the IM-LT3 FPGA and handles the majority of interrupts from the system. A substantial number of interrupts are reserved to maintain compatibility with other modules within the Integrator family. The PIC provides a set of registers to control and handle interrupts. These are described in Primary interrupt controller registers.

Secondary interrupt controller

The SIC is implemented in the baseboard PLD and combines interrupts from MMC socket, the UART ring indicator bits, and a software generated interrupt to the CPPLDINT input of the PIC.

The MMC interrupt on the SIC is generated by the card insertion detect switch and is different from the MMCI interrupts in the PIC generated by the MMCI PrimeCell.

The secondary controller provides a set of registers to control and handle interrupts. These are described in the Integrator/CP Baseboard User Guide.

Debug communications interrupts

The processor on the Core Tile incorporates EmbeddedICE hardware. This provides debug communications data read and write registers that are used to pass data between the processor and JTAG equipment. The COMMTX and COMMRX signals from the Core Tile are input to the debug comms interrupt controller. For a description of the debug communications channel, see the Technical Reference Manual for your core.

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