C.8.2. Interrupt routing

Figure C.11 shows a legacy CP system with Core Modules and Logic Modules. In this system the IRQ signals are rotated as they are routed from the modules to the interrupt controllers in the CP and Core Module.

Figure C.11. Interrupt signal routing with Core Module

Figure C.11 highlights how the signals are routed so that, for example, the interrupt request from logic module 2 connects to LM_INT2 (IRQ[2]) on the baseboard. A similar routing applies for logic module 1 and 3. The operation of the interrupts relies on the Core Module being mounted on the baseboard first with any logic modules on top.

Figure C.12 shows how interrupt signals are routed for a system consisting of an Integrator/CP, IM-LT3, Core Tile, and Logic Tile. The rotation of interrupt signals, if used, must be done in the Logic Tile FPGAs.

Figure C.12. Interrupt signal routing for tiles

The signals route through the SIC. Determining the source of an interrupt requires interrogating first the primary and then the secondary controller. The time required for the extra instructions might cause a problem with interrupt latency in some situations. To improve latency, FIQ[0] and IRQ[0] (as LM_LLINT[1:0]) are also routed to the PIC as well.

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