C.4.2. System controller FPGA

The system controller FPGA is located on the IM-LT3. It contains the main bus bridges, memory controllers, and peripheral controllers. Figure C.7 shows a simplified block diagram of a system controller FPGA.

Figure C.7. System controller FPGA block diagram

Note

The IM-LT3 FPGA must have an appropriate Integrator/CP-compatible image in order to control the peripherals on the Integrator/CP baseboard. Images are supplied for current CT7TDMI, CT926EJ-S, and CT1136JF-S Core Tiles.

The FPGA on the IM-LT3, and on Logic Tiles added to the system, share the open-collector signal GLOBAL_DONE. When the system is powered on, the FPGA loads a configuration from the configuration flash memory on the IM-LT3 into the configuration inputs of the FPGA. The GLOBAL_DONE signal is used by the FPGAs to signal that configuration is complete and system reset can be completed.

You can use Multi-ICE to reprogram the PLD, FPGA, and flash when the system is placed in configuration mode.

The IM-LT3 configuration flash can store up to four images, but only two are used in the PLD image loaded at manufacture. The images are selected by SW4[1] as described in PLD circuitry. The CFGSEL[1:0] signals from the baseboardare not used to select the image.

Copyright © 2005, 2006 ARM Limited. All rights reserved.ARM DUI 0216B
Non-Confidential