C.2. Module ID selection and interrupt routing

The Integrator/CP can only have one master module (immediately on the baseboard). The Core Tile and IM-LT3 combination give a Core Module ID of 0.

Note

The signals nPPRES[3:0] (Core Module present) are used to signal the presence of modules to the central decoder. The IM-LT3 drives these signals as b1110 to indicate that only one module is present.

The output from the secondary interrupt controller (SIC) is routed to the Primary Interrupt Controller (PIC) in the IM-LT3 FPGA. The PIC outputs directly drive the nFIQ and nIRQ inputs on the processor present on the Core Tile.

Copyright © 2005, 2006 ARM Limited. All rights reserved.ARM DUI 0216B
Non-Confidential