3.8.5. Integrated logic analyzer

The Inegrated logic analyzer connector J12 enables you to connect a compatible analyzer (such as ChipScope) to access the FPGA JTAG signals when the system is in debug mode (CONFIG link not fitted and a JTAG debugger is being used to examine code on a CPU).

If the board is in debug mode, the configuration scan chain is not normally accessible. The integrated logic analyzer connector, however, provides access to the IM-LT3 configuration scan chain and enables debugging of the IM-LT3 FPGA design and the software running on a Core Tile or Core Module simultaneously. For more details on the integrated logic analyzer, see the ChipScope details on the Xilinx website (www.xilinx.com).

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