Two Mictor connectors on the IM-LT3 enable monitoring of header signals by an external logic analyzer. Figure A.7 shows the pinout of the Mictor connectors.

Table A.6 lists the pinouts of debug connector J11. A logic analyzer can be attached to J11 to monitor signals YU[179:153]. If an SMM is implemented in the FPGA on an attached Logic Tile, signals YU[179:153] can be used as a trace port for the synthesized core. The Trace signal names in Table A.6 refer to the signal names typically used on trace connectors. The IM-LT3 signal names refer to the signals names used on the on the IM-LT3 schematic.

Table A.7 lists the pinouts of debug connector J4. A logic analyzer can be attached to J4 to monitor signals XU[179:146]. (These signals are present on the upper HDRX connector.)