C.1.1. Integrator/CP system buses

Figure C.2 shows how the external system bus and the internal buses connect the various boards together.

Figure C.2. Bus routing between CP baseboard, Core Tile, and IM-LT3

System bus routing and bus interfaces

The Integrator/CP, IM-LT3, and Core Tile use an AMBA system bus comprised of:

AHB system bus

This is the AHB bus within the IM-LT3 FPGA. The bus bridges in the IM-LT3 FPGA connect it to the AHB-Lite external system bus and to the APB peripheral bus.

For the CT926EJ-S or CT1136JF-S, the AHB bus from the Core Tile is directly connected to the AHB system bus in the FPGA. For the CT7TDMI, there is an AHB wrapper in the FPGA that translates between the native ARM7TDMI bus and the AHB processor bus.

AHB-Lite system bus

This is the external bus present on the HDRA and HDRB connectors. It connects the baseboard to the IM-LT3. The AHB-Lite system bus is a single-master bus with the processor core as sole bus master.

Peripheral bus

This is the APB bus present within the IM-LT3 FPGA. It connects the system bus to the APB peripherals and control registers.

APB peripheral bus

The APB is an AMBA-compliant bus optimized for minimum power and reduced interface complexity. It is used to interface peripherals, such as the UARTs and the Keyboard and Mouse Interface (KMI), that do not require the high performance of the AHB.

The AHB-APB bridge is an AHB slave that provides an interface between the high- speed AHB domain and the low-power APB domain. The APB is not pipelined. Wait states are added during transfers between the APB and AHB when the AHB is required to wait for the APB protocol.

Figure C.3 shows some example APB peripherals that are implemented using PrimeCell or ADK devices synthesized into the FPGA on the IM-LT3.

Figure C.3. APB peripherals

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