Integrator style connectors HDRA and HDRB on the bottom of the board

Versatile tile connectors HDRX, HDRY, and HDRZ on the top of the board

Xilinx Virtex II Field Programmable Gate-Array (FPGA). The content of the FPGA depends on the configuration image loaded, but a typical system implements memory controllers and peripherals and also provides the interface logic between the Integrator style headers and the tile headers.

Flash memory that contains the images for the FPGA. The image is selectable and loaded into the FPGA by the Programmable Logic Device (PLD).

JTAG connector and routing logic for ICE and FPGA image download

user LEDs and switches

Logic analyzer connectors:

2MB of 32-bit Synchronous Static RAM (SSRAM)

up to 256MB of 32-bit wide SDRAM (optional) plugged into the Dual In-line Memory Module (DIMM) socket

Power-on reset logic

clock generators.

FPGA

Memory

Clocks

Expansion headers

Test and debug interfaces

Power supplies.