4.3. Configuring the FPGA from flash

The flash memory can store two configurations for the XC2V2000 FPGA. The configuration image is selected according to the setting of FPGA image switch S4 as listed in Table 4.1.

Table 4.1. Image selection

FPGA IMAGE switch S4[1]FPGA IMAGE switch S4[2]Flash image used

Image LED

Image base addressDescription
OFFOFF0Unlit0x000000Use image 0


OFF1Lit0x200000Use image 1


0Unlit0x000000Use image 0



1Lit0x200000Use image 1

The FPGA_IMAGE signal that connects to the tile above is generated on the IM-LT3. If there is no motherboard present, it defaults to high.

See the application notes for a description of example images. See Downloading new the FPGA configurations into flash for details of loading new images into the configuration flash. See PLD circuitry for details of the configuration logic.


FPGA switch S4[2] is connected to the PLD, but is reserved for future use.

If an Integrator motherboard is present, the CFGSEL[1:0] signals will be b00, b01, or b10 depending on the type of motherboard. Pullup and pulldown resistors on the IM-LT3 drive CFGSEL[1:0] to b01 if no motherboard is connected. These signals are reserved for future use and do not affect image selection if you are using the PLD image that is loaded at manufacture.

The positions of the switches have no effect on the flash programming operation, only image selection on power-up.

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