4.1. FPGA configuration system architecture

At power-up the FPGA loads configuration data to its internal configuration memory. Figure 3.2 shows the architecture of the FPGA configuration system.

There are two ways to load the FPGA image:

Debug mode

The FPGA is configured from the flash memory using the select MAP mode of configuration.

This mode is the normal FPGA image loading mode. The loading process is managed by the configuration Programmable Logic Device (PLD). The flash must contain valid configuration data and the CONFIG link must not be fitted.

The flash memory can store two configuration images. The image is selected either by DIP switch S4[1] (see Configuring the FPGA from flash).

Configuration mode

The FPGA is configured directly by JTAG and uses the boundary scan mode of configuration. You can use the Multi-ICE JTAG port to download configurations when the CONFIG link is fitted (see Loading new FPGA configurations).

Note

You can also load a flash loading image into the FPGA and then use that image to control loading the flash memory itself with a new image.

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