A.4. HDRA Integrator connector

Figure A.3 shows the pin numbers of the HDRA socket.

Figure A.3. HDRA socket pin numbering

The signals are described in Table A.4.

Table A.4. Bus bit assignment

Pin label

AHB signal name

Description

A[31:0]HADDR[31:0]

System address bus

B[31:0]-Connected to FPGA
C[31:28]DBGXTRIG[3:0]Debug cross-trigger signals
C[27:16]

Not used

-

C15

HMASTLOCK

Locked transaction

C14HRESP1

Slave response

C13HRESP0

Slave response

C12

HREADY

Slave wait response

C11

HWRITE

Write transaction

C[10:8]

HPROT[2:0]

Transaction protection type

C[7:5]

HBURST[2:0]

Transaction burst size

C4HPROT[3]

Transaction protection type

C[3:2]

HSIZE[1:0]

Transaction width

C[1:0]

HTRAN[1:0]

Transaction type

D[31:0]HDATA[31:0]

System data bus

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