3.8.2. JTAG connection modes

The system is capable of operating in user mode or configuration mode.

Debug mode

Debug mode (sometimes also called user mode or normal mode) is selected by default (when a jumper is not fitted on the CONFIG link, see Figure 3.13). In this mode, the processor cores are accessible on the scan chain, as shown in Figure 3.15.

Configuration mode

In configuration mode, the configuration TAP controllers of all FPGAs and PLDs in the system are connected into the scan chain. This allows the board to be configured or upgraded using Multi-ICE or other JTAG debugging equipment.

To select configuration mode, fit a jumper to the CONFIG link on the IM-LT3 (see Figure 3.13). This has the effect of pulling the nCFGEN signal LOW and illuminating the CFGEN LED on the IM-LT3 and rerouting the JTAG scan path. The LED provides an indication that the development system is in the configuration mode.

After upgrading the flash FPGA images:

  1. Remove the CONFIG link.

  2. Power cycle the development system.

The configuration mode allows FPGA and PLD code to be updated as follows:

  • The FPGAs are volatile, but load their configuration from flash memory. Flash memory does not have a JTAG port, but it can be programmed by loading designs into the FPGAs and PLDs that handle the transfer of data to the flash using JTAG.

  • The PLDs are nonvolatile devices that can be programmed directly by JTAG.

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