3.2. FPGA

The IM-LT3 FPGA provides sufficient functionality for the IM-LT3 to operate as a standalone development system. The IM-LT3 can also be used with an Integrator/CP baseboard to provide interface to Core Modules, Logic Tiles, and Core Tiles.

If you are using the IM-LT3 with an Integrator baseboard, the system bus arbitration, system interrupt control, and input/output resources are provided by the system controller FPGA on the baseboard. See the user guide for your baseboard for further information.

Figure 3.1 illustrates the function of the IM-LT3 FPGA and shows how it connects to the other devices in the system.

At power-up the FPGA loads its configuration data from a flash memory device. Parallel data from the flash is streamed by the Programmable Logic Device (PLD) into the configuration ports of the FPGA. See PLD circuitry for details of the FPGA configuration mechanism. The FPGA contains an image encryption key stored in volatile memory. A backup battery provides power to the key memory. If the battery is removed or shorted, the encryption key will be erased and the FPGA image cannot be loaded.

The JTAG interface can be used to reprogram the PLD, FPGA, and flash when the system is placed in configuration mode. See JTAG support.

Figure 3.1. IM-LT3 block diagram

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