C.8.3. CP image interrupt control registers

The baseboard FPGA provides an interrupt controller to handle IRQs and FIQs from around the system. These are in addition to the primary IM-LT3 interrupt controller, and are described in:

Primary interrupt controller registers

The CP image for the FPGA provides interrupt controllers for both IRQs and FIQs that maintain compatibility with other Integrator modules to ensure code portability. The primary interrupt control registers are listed in Table C.9

Table C.9. Primary interrupt register addresses

Address

Name

Type

Size

Function

0x14000000

PIC_IRQ_STATUS

Read

22

IRQ gated interrupt status

0x14000004

PIC_IRQ_RAWSTAT

Read

22

IRQ raw interrupt status

0x14000008

PIC_IRQ_ENABLESET

Read/write

22

IRQ enable set

0x1400000C

PIC_IRQ_ENABLECLR

Write

22

IRQ enable clear

0x14000010

PIC_INT_SOFTSET

Read/write

16

Software interrupt set

0x14000014

PIC_INT_SOFTCLR

Write

16

Software interrupt clear

0x14000020

PIC_FIQ_STATUS

Read-only

22

FIQ gated interrupt status

0x14000024

PIC_FIQ_RAWSTAT

Read-only

22

FIQ raw interrupt status

0x14000028

PIC_FIQ_ENABLESET

Read/write

22

FIQ enable set

0x1400002C

PIC_FIQ_ENABLECLR

Write-only

22

FIQ enable clear

The bit assignment for interrupts in the status, raw status, and enable registers for the IRQ and FIQ interrupt controllers is similar and is shown in Table C.10.

Table C.10. Primary interrupt register bit assignments

Bit

Name

Function

[31:29]-Reserved
[28]TS_PENINTTouchscreen pen-down event interrupt
[27]ETH_INTEthernet interface interrupt
[26]CPPLDINTInterrupt from secondary interrupt controller, see Secondary interrupt controller registers.
[25]AACIINTAudio interface interrupt
[24]MMCIINT1MultiMedia card interface
[23]MMCIINT0MultiMedia card interface

[22]

CLCDCINT

Display controller interrupt

[21:11]

-Reserved

[10]

LM_LLINT1

Logic module low-latency interrupt 1(from Logic Tiles mounted above the IM-LT3)

[9]

LM_LLINT0

Logic module low-latency interrupt 0 (from Logic Tiles mounted above the IM-LT3)

[8]

RTCINT

Real time clock interrupt

[7]

TIMERINT2

Counter-timer 2 interrupt

[6]

TIMERINT1

Counter-timer 1 interrupt

[5]

TIMERINT0

Counter-timer 0 interrupt

[4]

MOUSEINT

Mouse interrupt

[3]

KBDINT

Keyboard interrupt

[2]

UARTINT1

UART 1 interrupt

[1]

UARTINT0

UART 0 interrupt

[0]

SOFTINT

Software interrupt

Debug communications interrupt registers

The bit assignments for the IRQ and FIQ status, raw status and enable register are shown in Table C.11.

Table C.11. IRQ and FIQ register bit assignment

Bit

Name

Function

[31:3]ReservedWrite as 0. Reads undefined.
[2]

COMMTx

Debug communications transmit interrupt.

This interrupt indicates that the communications channel is available for the processor to pass messages to the debugger.

[1]

COMMRx

Debug communications receive interrupt.

This interrupt indicates to the processor that messages are available for the processor to read.

[0]

SOFT

Software interrupt.

Secondary interrupt controller registers

The secondary interrupt control registers are listed in Table C.12.

Table C.12. Secondary interrupt register addresses

Address

Name

Type

Size

Function

0xCA000000

SIC_IRQ_STATUS

Read

22

SIC gated interrupt status

0xCA000004

SIC_IRQ_RAWSTAT

Read

22

SIC raw interrupt status

0xCA000008

SIC_IRQ_ENABLESET

Read/write

22

SIC enable set

0xCA00000C

SIC_IRQ_ENABLECLR

Write

22

SIC enable clear

0xCA000010

SIC_INT_SOFTSET

Read/write

16

Software interrupt set

0xCA000014

SIC_INT_SOFTCLR

Write

16

Software interrupt clear

For more details, see the Integrator/CP Baseboard User Guide.

Soft interrupt set and soft interrupt clear registers

The primary, secondary, and comms interrupt controllers provide a register for controlling and clearing software interrupts.

This register is accessed using the software interrupt set and software interrupt clear locations. The set and clear locations are used as follows:

  • Set the software interrupt by writing to the CM_SOFT_INTSET location:

    • write a 1 to SET the software interrupt

    • write a 0 to leave the software interrupt unchanged.

  • Read the current state of the software interrupt register from the CM_SOFT_INTSET location. A bit set to 1 indicates that the corresponding interrupt request is active.

  • Clear the software interrupt by writing to the CM_SOFT_INTCLR location:

    • write a 1 to CLEAR the software interrupt

    • write a 0 to leave the software interrupt unchanged.

The bit assignment for the software interrupt register is shown in Table C.13.

Table C.13. IRQ register bit assignment

Bit

Name

Function

[31:1]ReservedWrite as 0. Reads undefined.
[0]

SOFT

Software interrupt

Note

The software interrupt described in this section is used by software to generate IRQs or FIQs. It must not be confused with the ARM SWI software interrupt instruction. See the ARM Architecture Reference Manual.

Refer to the documentation supplied with your Core Module for details on Core Module registers.

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