A.5.1. HDRB signal descriptions

Table A.5 describes the signals for an AMBA AHB system bus on an Integrator motherboard. If the signal also connects to a tile header, the tile signal name is shown in parentheses. See also Isolation of HDRZ signals.

Table A.5. HDRB signal description (AHB)

Pin label

Integrator signal name

Description

E[31:28]

SYSCLK[3:0]

System clocks. The source of the clocks depend on the image loaded into the FPGA and the attached boards.

E[27:24]

nPPRES[3:0]

Processor present (YU[123:120])

E[23:20]

nIRQ[3:0]

Interrupt request to processors 3, 2, 1, and 0 respectively (YU[119:116])

E[19:16]

nFIQ[3:0]

Fast interrupt requests to processors 3, 2, 1, and 0 respectively (YU[115:112])

E[15:12]

ID[3:0]

Core tile stack position indicator (YU[111:108])

E[11:8]HLOCK[3:0]

System bus lock from processor 3, 2, 1, and 0 respectively (YU[107:104])

E[7:4]

HGRANT[3:0]

System bus grant to processor 3, 2, 1, and 0 respectively (YU[103:100])

E[3:0]

HBUSREQ[3:0]

System bus request from processors 3, 2, 1, and 0 respectively (YU[99:96])

F[31:0]

-

YU[95:64]
G16

nRTCKEN

RTCK AND gate enable

G[15:14]

CFGSEL[1:0]

FPGA configuration select

G13

nCFGEN

Sets motherboard into configuration mode

G12

nSRST

Multi-ICE reset (open collector)

G11

FPGADONE

Indicates when FPGA configuration is complete (open collector). This signal is connected to the tile signal GLOBAL_DONE.

G10

RTCK

Returned JTAG test clock

G9

nSYSRST

Buffered system reset

G8

nTRST

JTAG reset

G7

TDO

JTAG test data out

G6

TDI

JTAG test data in

G5

TMS

JTAG test mode select

G4

TCK

JTAG test clock

G[3:1]

MASTER[2:0]

Master ID. Binary encoding of the master currently performing a transfer on the bus. Corresponds to the tile ID and to the HBUSREQ and HGRANT line numbers. (YU[127:125])

G0

nMBDET

Motherboard detect pin (YU[124])

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