C.7.1. Reset control signals

Table C.8 describes the external reset signals.

Table C.8. Reset signal descriptions

Name

Description

Type

Function

ARM_nPORESET

Processor reset

Output

The ARM_nPORESET signal is used to reset the processor core. It is generated from nSRST LOW when the Core Tile is used standalone, or nSYSRST LOW when the Core Tile is attached to a motherboard.

PBRST

Push-button reset

Input

The PBRST signal is generated by pressing the reset button.

nSRST

System reset

Bidirectional

The nSRST open collector output signal is driven LOW by the IM-LT3 FPGA when the signal PBRST or software reset (SWRST) is asserted.

As an input, nSRST can be driven LOW by Multi-ICE.

If there is no motherboard present, the nSRST signal is synchronized to the processor bus clock to generate the ARM_nPORESET signal.

nSYSRST

System reset

Output

The nSYSRST signal is generated by the system controller FPGA on the IM-LT3. It is used to generate HRESETn to the Core Tile and the system.

Copyright © 2005, 2006 ARM Limited. All rights reserved.ARM DUI 0216B
Non-Confidential